SCDS402B June   2019  – February 2024 TMUX1136

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics (VDD = 5V ±10 %)
    6. 5.6 Electrical Characteristics (VDD = 3.3V ±10 %)
    7. 5.7 Electrical Characteristics (VDD = 1.8V ±10 %)
    8. 5.8 Electrical Characteristics (VDD = 1.2V ±10 %)
    9.     Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 On-Resistance
    2. 6.2 Off-Leakage Current
    3. 6.3 On-Leakage Current
    4. 6.4 Transition Time
    5. 6.5 Break-Before-Make
    6. 6.6 Charge Injection
    7. 6.7 Off Isolation
    8. 6.8 Crosstalk
    9. 6.9 Bandwidth
  8. 7 Detailed Description
    1. 7.1 Functional Block Diagram
    2. 7.2 Feature Description
      1. 7.2.1 Bidirectional Operation
      2. 7.2.2 Rail to Rail Operation
      3. 7.2.3 1.8V Logic Compatible Inputs
      4. 7.2.4 Fail-Safe Logic
      5. 7.2.5 Ultra-low Leakage Current
      6. 7.2.6 Ultra-low Charge Injection
    3. 7.3 Device Functional Modes
      1. 7.3.1 Truth Tables
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DGS|10
  • DQA|10
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.2.6 Ultra-low Charge Injection

The TMUX1136 has a transmission gate topology, as shown in Figure 7-3. Any mismatch in the stray capacitance associated with the NMOS and PMOS causes an output level change whenever the switch is opened or closed.

GUID-0040BE35-F6FB-448D-80DC-8147652BDD3F-low.gifFigure 7-3 Transmission Gate Topology

The TMUX1136 has special charge-injection cancellation circuitry that reduces the drain-to-source charge injection to -6pC at VD = 1V as shown in Figure 7-4.

GUID-247B3929-CAF1-423D-8245-19C799CAF810-low.gifFigure 7-4 Charge Injection vs Drain Voltage