The TMUX1208 and TMUX1209 are general purpose complementary metal-oxide semiconductor (CMOS) multiplexers (MUX). The TMUX1208 offers 8:1 single-ended channels, while the TMUX1209 offers differential 4:1 or dual 4:1 single-ended channels. Wide operating supply of 1.08 V to 5.5 V allows for use in a broad array of applications from personal electronics to building automation applications. The device supports bidirectional analog and digital signals on the source (Sx) and drain (D) pins ranging from GND to VDD.
All logic inputs have 1.8 V logic compatible thresholds, ensuring both TTL and CMOS logic compatibility when operating in the valid supply voltage range. Fail-Safe Logic circuitry allows voltages on the control pins to be applied before the supply pin, protecting the device from potential damage.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TMUX1208
TMUX1209 |
TSSOP (16) | 5.00 mm × 4.40 mm |
QFN (16) | 2.60 mm x 1.80 mm |
SPACER
Changes from B Revision (November 2018) to C Revision
Changes from A Revision (September 2018) to B Revision
Changes from * Revision (August 2018) to A Revision
PRODUCT | DESCRIPTION | |
---|---|---|
TMUX1208 | 8:1, 1-Channel, single-ended multiplexer | |
TMUX1209 | 4:1, 2-Channel, differential multiplexer |
PIN | TYPE(1) | DESCRIPTION | ||
---|---|---|---|---|
NAME | TSSOP | UQFN | ||
A0 | 1 | 15 | I | Address line 0. Controls the switch configuration as shown in Table 1. |
EN | 2 | 16 | I | Active high logic input. When this pin is low, all switches are turned off. When this pin is high, the A[2:0] address inputs determine which switch is turned on. |
N.C. | 3 | 1 | Not Connected | Not Connected |
S1 | 4 | 2 | I/O | Source pin 1. Can be an input or output. |
S2 | 5 | 3 | I/O | Source pin 2. Can be an input or output. |
S3 | 6 | 4 | I/O | Source pin 3. Can be an input or output. |
S4 | 7 | 5 | I/O | Source pin 4. Can be an input or output. |
D | 8 | 6 | I/O | Drain pin. Can be an input or output. |
S8 | 9 | 7 | I/O | Source pin 8. Can be an input or output. |
S7 | 10 | 8 | I/O | Source pin 7. Can be an input or output. |
S6 | 11 | 9 | I/O | Source pin 6. Can be an input or output. |
S5 | 12 | 10 | I/O | Source pin 5. Can be an input or output. |
VDD | 13 | 11 | P | Positive power supply. This pin is the most positive power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND. |
GND | 14 | 12 | P | Ground (0 V) reference |
A2 | 15 | 13 | I | Address line 2. Controls the switch configuration as shown in Table 1. |
A1 | 16 | 14 | I | Address line 1. Controls the switch configuration as shown in Table 1. |
PIN | TYPE(1) | DESCRIPTION | ||
---|---|---|---|---|
NAME | TSSOP | UQFN | ||
A0 | 1 | 15 | I | Address line 0. Controls the switch configuration as shown in Table 2. |
EN | 2 | 16 | I | Active high logic input. When this pin is low, all switches are turned off. When this pin is high, the A[1:0] address inputs determine which switch is turned on. |
N.C. | 3 | 1 | Not Connected | Not Connected |
S1A | 4 | 2 | I/O | Source pin 1A. Can be an input or output. |
S2A | 5 | 3 | I/O | Source pin 2A. Can be an input or output. |
S3A | 6 | 4 | I/O | Source pin 3A. Can be an input or output. |
S4A | 7 | 5 | I/O | Source pin 4A. Can be an input or output. |
DA | 8 | 6 | I/O | Drain pin A. Can be an input or output. |
DB | 9 | 7 | I/O | Drain pin B. Can be an input or output. |
S4B | 10 | 8 | I/O | Source pin 4B. Can be an input or output. |
S3B | 11 | 9 | I/O | Source pin 3B. Can be an input or output. |
S2B | 12 | 10 | I/O | Source pin 2B. Can be an input or output. |
S1B | 13 | 11 | I/O | Source pin 1B. Can be an input or output. |
VDD | 14 | 12 | P | Positive power supply. This pin is the most positive power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND. |
GND | 15 | 13 | P | Ground (0 V) reference |
A1 | 16 | 14 | I | Address line 1. Controls the switch configuration as shown in Table 2. |