SCDS476 June   2024 TMUX1308A-Q1 , TMUX1309A-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Thermal Information: TMUX1308A-Q1
    4. 6.4  Thermal Information: TMUX1309A-Q1
    5. 6.5  Recommended Operating Conditions
    6. 6.6  Electrical Characteristics
    7. 6.7  Logic and Dynamic Characteristics
    8. 6.8  Timing Characteristics
    9. 6.9  Injection Current Coupling
    10. 6.10 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1  On-Resistance
    2. 7.2  Off-Leakage Current
    3. 7.3  On-Leakage Current
    4. 7.4  Transition Time
    5. 7.5  Break-Before-Make
    6. 7.6  tON(EN) and tOFF(EN)
    7. 7.7  Charge Injection
    8. 7.8  Off Isolation
    9. 7.9  Crosstalk
    10. 7.10 Bandwidth
    11. 7.11 Injection Current Control
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Bidirectional Operation
      2. 8.3.2 Rail-to-Rail Operation
      3. 8.3.3 1.8V Logic Compatible Inputs
      4. 8.3.4 Fail-Safe Logic
      5. 8.3.5 High-Impedance Optimization
      6. 8.3.6 Injection Current Control
        1. 8.3.6.1 TMUX13xxA-Q1 is Powered, Channel is Unselected, and the Input Signal is Greater Than VDD (VDD = 5V, VINPUT = 5.5V)
        2. 8.3.6.2 TMUX13xxA-Q1 is Powered, Channel is Selected, and the Input Signal is Greater Than VDD (VDD = 5V, VINPUT = 5.5V)
        3. 8.3.6.3 TMUX13xxA-Q1 is Unpowered and the Input Signal has a Voltage Present (VDD = 0V, VINPUT = 3V)
    4. 8.4 Device Functional Modes
    5. 8.5 Truth Tables
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Short To Battery Protection
      4. 9.2.4 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information
  13. 12Revision History

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDD Supply voltage 1.62 5.5 V
VS or VD Signal path input/output voltage (source or drain pin) (Sx, D) 0 VDD V
VSEL or VEN Logic control input pin voltage (EN, A0, A1, A2) 0 5.5 V
IS or ID (CONT) Continuous current through switch (Sx, D pins) –40°C to +85°C –50 50 mA
IS or ID (CONT) Continuous current through switch (Sx, D pins) –40°C to +125°C –25 25 mA
IOK Current per input into source or drain pins when singal voltage exceeds recommended operating voltage (1) –50 50 mA
IINJ Injected current into single off switch input –50 50 mA
IINJ_ALL Total injected current into all off switch inputs combined –100 100 mA
TA Ambient temperature –40 125 °C
(1) If source or drain voltage exceeds VDD, or goes below GND, the pin will be shunted to GND through an internal FET, the current must be limited within the specified value. If Vsignal > VDD or if Vsignal < GND.