SCDS403C february   2021  – july 2023 TMUX7308F , TMUX7309F

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Thermal Information
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Electrical Characteristics (Global)
    6. 7.6  ±15 V Dual Supply: Electrical Characteristics
    7. 7.7  ±20 V Dual Supply: Electrical Characteristics
    8. 7.8  12 V Single Supply: Electrical Characteristics
    9. 7.9  36 V Single Supply: Electrical Characteristics
    10. 7.10 Typical Characteristics
  9. 8 Parameter Measurement Information
    1. 8.1  On-Resistance
    2. 8.2  Off-Leakage Current
    3. 8.3  On-Leakage Current
    4. 8.4  Input and Output Leakage Current Under Overvoltage Fault
    5. 8.5  Break-Before-Make Delay
    6. 8.6  Enable Delay Time
    7. 8.7  Transition Time
    8. 8.8  Fault Response Time
    9. 8.9  Fault Recovery Time
    10. 8.10 Charge Injection
    11. 8.11 Off Isolation
    12. 8.12 Crosstalk
    13. 8.13 Bandwidth
    14. 8.14 THD + Noise
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Flat On – Resistance
      2. 9.3.2 Protection Features
        1. 9.3.2.1 Input Voltage Tolerance
        2. 9.3.2.2 Powered-Off Protection
        3. 9.3.2.3 Fail-Safe Logic
        4. 9.3.2.4 Overvoltage Protection and Detection
        5. 9.3.2.5 Adjacent Channel Operation During Fault
        6. 9.3.2.6 ESD Protection
        7. 9.3.2.7 Latch-Up Immunity
        8. 9.3.2.8 EMC Protection
      3. 9.3.3 Bidirectional Operation
      4. 9.3.4 1.8 V Logic Compatible Inputs
      5. 9.3.5 Integrated Pull-Down Resistor on Logic Pins
    4. 9.4 Device Functional Modes
      1. 9.4.1 Normal Mode
      2. 9.4.2 Fault Mode
      3. 9.4.3 Truth Tables
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

GUID-243DF65E-318D-47B1-A675-6DAB07CC026A-low.gifFigure 6-1 PW Package, 16-Pin TSSOP (Top View)
GUID-0B7D6564-8522-4F06-806F-DF02C1CE794D-low.gifFigure 6-2 RRP Package, 16-Pin WQFN (Top View)
Table 6-1 Pin Functions: TMUX7308F
PIN TYPE(1) DESCRIPTION
NAME TSSOP WQFN
A0 1 15 I Logic control input address 0 (A0), has internal 4 MΩ pull-down resistor. Controls switch state as shown in Section 9.4.3.
EN 2 16 I Active high logic enable (EN) pin, has internal 4 MΩ pull-down resistor. The device is disabled and all switches become high impedance when the pin is low. When the pin is high, the Ax logic inputs determine individual switch states as shown in Section 9.4.3.
VSS 3 1 P Negative power supply. This pin is the most negative power-supply potential. In single-supply applications, this pin can be connected to ground. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VSS and GND.
S1 4 2 I/O Overvoltage protected source pin 1. Can be an input or output.
S2 5 3 I/O Overvoltage protected source pin 2. Can be an input or output.
S3 6 4 I/O Overvoltage protected source pin 3. Can be an input or output.
S4 7 5 I/O Overvoltage protected source pin 4. Can be an input or output.
D 8 6 I/O Drain pin. Can be an input or output. The drain pin is not overvoltage protected.
S8 9 7 I/O Overvoltage protected source pin 8. Can be an input or output.
S7 10 8 I/O Overvoltage protected source pin 7. Can be an input or output.
S6 11 9 I/O Overvoltage protected source pin 6. Can be an input or output.
S5 12 10 I/O Overvoltage protected source pin 5. Can be an input or output.
VDD 13 11 P Positive power supply. This pin is the most positive power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
GND 14 12 P Ground (0 V) reference
A2 15 13 I Logic control input address 2 (A2), has internal 4 MΩ pull-down resistor. Controls switch state as shown in Section 9.4.3.
A1 16 14 I Logic control input address 1 (A1), has internal 4 MΩ pull-down resistor. Controls switch state as shown in Section 9.4.3.
Thermal Pad P The thermal pad is not connected internally. It is recommended that the pad be tied to GND or VSS for best performance.
(1) I = input, O = output, I/O = input and output, P = power
GUID-E56CE380-9036-490B-8E0F-93FC91F6572F-low.gifFigure 6-3 PW Package, 16-Pin TSSOP (Top View)
GUID-141F0D0F-7C1E-4CD7-97D1-26F0D4E03249-low.gifFigure 6-4 RRP Package, 16-Pin WQFN (Top View)
Table 6-2 Pin Functions: TMUX7309F
PIN TYPE(1) DESCRIPTION
NAME TSSOP WQFN
A0 1 15 I Logic control input address 0 (A0), has internal 4 MΩ pull-down resistor. Controls switch state as shown in Section 9.4.3.
EN 2 16 I Active high logic enable (EN) pin, has internal 4 MΩ pull-down resistor. The device is disabled and all switches become high impedance when the pin is low. When the pin is high, the Ax logic inputs determine individual switch states as shown in Section 9.4.3.
VSS 3 1 P Negative power supply. This pin is the most negative power-supply potential. In single-supply applications, this pin can be connected to ground. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VSS and GND.
S1A 4 2 I/O Overvoltage protected source pin 1A. Can be an input or output.
S2A 5 3 I/O Overvoltage protected source pin 2A. Can be an input or output.
S3A 6 4 I/O Overvoltage protected source pin 3A. Can be an input or output.
S4A 7 5 I/O Overvoltage protected source pin 4A. Can be an input or output.
DA 8 6 I/O Drain terminal A. Can be an input or output. The drain pin is not overvoltage protected.
DB 9 7 I/O Drain terminal B. Can be an input or output. The drain pin is not overvoltage protected.
S4B 10 8 I/O Overvoltage protected source pin 4B. Can be an input or output.
S3B 11 9 I/O Overvoltage protected source pin 3B. Can be an input or output.
S2B 12 10 I/O Overvoltage protected source pin 2B. Can be an input or output.
S1B 13 11 I/O Overvoltage protected source pin 1B. Can be an input or output.
VDD 14 12 P Positive power supply. This pin is the most positive power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
GND 15 13 P Ground (0 V) reference
A1 16 14 I Logic control input address 1 (A1), has internal 4 MΩ pull-down resistor. Controls switch state as shown in Section 9.4.3.
Thermal Pad P The thermal pad is not connected internally. It is recommended that the pad be tied to GND or VSS for best performance.
(1) I = input, O = output, I/O = input and output, P = power