SCDS459A October   2022  – November 2022 TMUX7436F

PRODMIX  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Thermal Information
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Electrical Characteristics: Global
    6. 6.6  ±15 V Dual Supply: Electrical Characteristics
    7. 6.7  ±20 V Dual Supply: Electrical Characteristics
    8. 6.8  12 V Single Supply: Electrical Characteristics
    9. 6.9  36 V Single Supply: Electrical Characteristics
    10. 6.10 Typical Characteristics
  7. Parameter Measurement Information
    1. 7.1  On-Resistance
    2. 7.2  Off-Leakage Current
    3. 7.3  On-Leakage Current
    4. 7.4  Input and Output Leakage Current Under Overvoltage Fault
    5. 7.5  Enable Delay Time
    6. 7.6  Break-Before-Make Delay
    7. 7.7  Transition Time
    8. 7.8  Fault Response Time
    9. 7.9  Fault Recovery Time
    10. 7.10 Fault Flag Response Time
    11. 7.11 Fault Flag Recovery Time
    12. 7.12 Charge Injection
    13. 7.13 Off Isolation
    14. 7.14 Crosstalk
    15. 7.15 Bandwidth
    16. 7.16 THD + Noise
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Flat ON-Resistance
      2. 8.3.2 Protection Features
        1. 8.3.2.1 Input Voltage Tolerance
        2. 8.3.2.2 Powered-Off Protection
        3. 8.3.2.3 Fail-Safe Logic
        4. 8.3.2.4 Overvoltage Protection and Detection
        5. 8.3.2.5 Adjacent Channel Operation During Fault
        6. 8.3.2.6 ESD Protection
        7. 8.3.2.7 Latch-Up Immunity
        8. 8.3.2.8 EMC Protection
      3. 8.3.3 Overvoltage Fault Flags
      4. 8.3.4 Bidirectional Operation
      5. 8.3.5 1.8 V Logic Compatible Inputs
      6. 8.3.6 Integrated Pull-Down Resistor on Logic Pins
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Mode
      2. 8.4.2 Fault Mode
      3. 8.4.3 Truth Tables
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Overvoltage Protection and Detection

The TMUX7436F detects overvoltage inputs by comparing the voltage on a source pin (Sx) with the supplies (VDD and VSS). A signal is considered overvoltage if it exceeds the supply voltages by the threshold voltage (VT).

The switch automatically turns OFF regardless of the logic controls when an overvoltage is detected. The source pin becomes high impedance and ensures only small leakage current flows through the switch. The drain pin (Dx) behavior can be adjusted by controlling the drain response (DR) pin in the following ways:

  1. DR pin floating or driven above VIH:

    If the DR pin is driven above VIH level of the pin, then the drain pin becomes high impedance (Hi-Z) upon overvoltage fault.

  2. DR driven below VIL:

    If the DR pin is driven below VIL level of the pin, and the channel expeirencing the overvoltage fault condition is currently being selected by the logic controls (EN, SELx), then the drain pin (Dx) is pulled to the supply that was exceeded through a 40 kΩ resistor. For example, if the source voltage exceeds VDD, then the drain output is pulled to VDD. If the source voltage exceeds VSS, then the drain output is pulled to VSS. The pull-up/pull-down impedance is approximately 40 kΩ, and as a result, the drain current is limited during a shorted load (to GND) condition.

Figure 8-1 shows a detailed view of the how the DR pin, SELx pin, and EN pin controls the output state of the drain pin under a fault scenario.

Figure 8-1 Detailed Functional Diagram