SCDS435B september 2021 – august 2023 TMUX8108 , TMUX8109
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
PIN | TYPE(1) | DESCRIPTION | ||
---|---|---|---|---|
NAME | TSSOP | WQFN | ||
A0 | 1 | 15 | I | Logic control input address 0 (A0). |
EN | 2 | 16 | I | Active high digital enable (EN) pin. The device is disabled and all switches become high impedance when the pin is low. When the pin is high, the Ax logic inputs determine individual switch states. |
VSS | 3 | 1 | P | Negative power supply. This pin is the most negative power-supply potential. In single-supply applications, this pin can be connected to ground. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VSS and GND. |
S1 | 4 | 2 | I/O | Source pin 1. Can be an input or output. |
S2 | 5 | 3 | I/O | Source pin 2. Can be an input or output. |
S3 | 6 | 4 | I/O | Source pin 3. Can be an input or output. |
S4 | 7 | 5 | I/O | Source pin 4. Can be an input or output. |
D | 8 | 6 | I/O | Drain pin. Can be an input or output. |
S8 | 9 | 7 | I/O | Source pin 8. Can be an input or output. |
S7 | 10 | 8 | I/O | Source pin 7. Can be an input or output. |
S6 | 11 | 9 | I/O | Source pin 6. Can be an input or output. |
S5 | 12 | 10 | I/O | Source pin 5. Can be an input or output. |
VDD | 13 | 11 | P | Positive power supply. This pin is the most positive power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND. |
GND | 14 | 12 | P | Ground (0 V) reference |
A2 | 15 | 13 | I | Logic control input address 2 (A2). |
A1 | 16 | 14 | I | Logic control input address 1 (A1). |
Thermal Pad | — | The thermal pad is not connected internally. It is recommended to tie the pad to GND or VSS for the best performance. |
PIN | TYPE(1) | DESCRIPTION | ||
---|---|---|---|---|
NAME | TSSOP | WQFN | ||
A0 | 1 | 15 | I | Logic control input address 0 (A0). |
EN | 2 | 16 | I | Active high digital enable (EN) pin. The device is disabled and all switches become high impedance when the pin is low. When the pin is high, the Ax logic inputs determine individual switch states. |
VSS | 3 | 1 | P | Negative power supply. This pin is the most negative power-supply potential. In single-supply applications, this pin can be connected to ground. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VSS and GND. |
S1A | 4 | 2 | I/O | Source pin 1A. Can be an input or output. |
S2A | 5 | 3 | I/O | Source pin 2A. Can be an input or output. |
S3A | 6 | 4 | I/O | Source pin 3A. Can be an input or output. |
S4A | 7 | 5 | I/O | Source pin 4A. Can be an input or output. |
DA | 8 | 6 | I/O | Drain terminal A. Can be an input or output. |
DB | 9 | 7 | I/O | Drain terminal B. Can be an input or output |
S4B | 10 | 8 | I/O | Source pin 4B. Can be an input or output. |
S3B | 11 | 9 | I/O | Source pin 3B. Can be an input or output. |
S2B | 12 | 10 | I/O | Source pin 2B. Can be an input or output. |
S1B | 13 | 11 | I/O | Source pin 1B. Can be an input or output. |
VDD | 14 | 12 | P | Positive power supply. This pin is the most positive power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND. |
GND | 15 | 13 | P | Ground (0 V) reference |
A1 | 16 | 14 | I | Logic control input address 1 (A1). |
Thermal Pad | — | The thermal pad is not connected internally. It is recommended to tie the pad to GND or VSS for the best performance. |