SCDS435B september 2021 – august 2023 TMUX8108 , TMUX8109
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
Latch-up is a condition where a low impedance path is created between a supply pin and ground. This condition is caused by a trigger (current injection or overvoltage), but once activated the low impedance path remains even after the trigger is no longer present. This low impedance path may cause system upset or catastrophic damage due to excessive current levels. The latch-up condition typically requires a power cycle to eliminate the low impedance path.
In the TMUX8108 and TMUX8109 devices, an insulating oxide layer is placed on top of the silicon substrate to prevent any parasitic junctions from forming. As a result, the devices are latch-up immune under all circumstances by device construction.
The TMUX8108 and TMUX8109 devices are constructed on silicon on insulator (SOI) based process where an oxide layer is added between the PMOS and NMOS transistor of each CMOS switch to prevent parasitic structures from forming. The oxide layer is also known as an insulating trench and prevents triggering of latch up events due to overvoltage or current injections. The latch-up immunity feature allows the TMUX8108 and TMUX8109 to be used in harsh environments. For more information on latch-up immunity refer to Using Latch Up Immune Multiplexers to Help Improve System Reliability.