SCDS436 September   2023 TMUX9616

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Thermal Information
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Electrical Characteristics: TMUX9616
    6. 6.6 Switching Characteristics: TMUX9616
    7. 6.7 Digital Timings: TMUX9616
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Off-Leakage Current
    2. 7.2 Device Turn On/Off Time
    3. 7.3 Off Isolation
    4. 7.4 Inter-Channel Crosstalk
    5. 7.5 Output Voltage Spike
    6. 7.6 Switch DC Offset Voltage
    7. 7.7 Isolation Diode Current
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Wide Input Signal Range (up to ±110 V, 220 VPP)
      2. 8.3.2 Bidirectional Operation
      3. 8.3.3 Device Digital Logic Control
      4. 8.3.4 Latch-Up Immunity by Device Construction
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Mode
      2. 8.4.2 Device Power Up
    5. 8.5 Device Logic Table
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4.2 Device Power Up

TMUX9616 will be powered up once VLL, VDD, and VSS reach their final voltage. VLL, VDD, and VSS can be powered up in any order (there is no power sequencing requirement). The device digital logic control will not receive updates until both VLL, VDD, and VSS are powered up. Additionally, after VLL, VDD, and VSS are powered up, the system FPGA or controller should wait at least 500 μs until writing to the device digital logic control. For more details on the device digital logic control, see the Device Digital Logic Control section.

On power-up, all 16 switches in TMUX9616 will be in the OFF state.