SLASEP7A May   2020  – May 2022 TMUXHS4212

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 High-Speed Performance Parameters
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Output Enable and Power Savings
      2. 8.3.2 Data Line Biasing
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 USB 3.2 Implementation for USB Type-C
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 PCIe Lane Muxing
        1. 9.2.2.1 Application Curves
    3. 9.3 Systems Examples
      1. 9.3.1 USB/eSATA
      2. 9.3.2 MIPI Camera Serial Interface
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

Figure 5-1 RKS Package, 20-Pin VQFN (Top View)
Table 5-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
A0n 4 I/O Port A, channel 0, high-speed negative signal
A0p 3 I/O Port A, channel 0, high-speed positive signal
A1n 8 I/O Port A, channel 1, high-speed negative signal
A1p 7 I/O Port A, channel 1, high-speed positive signal
B0n 18 I/O Port B, channel 0, high-speed negative signal (connector side)
B0p 19 I/O Port B, channel 0, high-speed positive signal (connector side)
B1n 16 I/O Port B, channel 1, high-speed negative signal
B1p 17 I/O Port B, channel 1, high-speed positive signal
C0n 14 I/O Port C, channel 0, high-speed negative signal
C0p 15 I/O Port C, channel 0, high-speed positive signal
C1n 12 I/O Port C, channel 1, high-speed negative signal
C1p 13 I/O Port C, channel 1, high-speed positive signal
GND 5, 11, 20 G Ground
OEn 2 I Active-low chip enable. The pin can be connected to GND if always on functional behavior is desired.
L: Normal operation, H: Shutdown. If always ON, behavior of the device is desired. The pin can be permanently connected to GND.
RSVD1 1 NA Reserved pins. Connect both pins to VCC
RSVD2 10 NA
SEL 9 I Port select pin.
L: Port A to Port B, H: Port A to Port C
VCC 6 P 3.3 V or 1.8 V power
(1) I = input, O = output, G = ground, P = power