SLOS528F July   2009  – April 2017 TPA3110D2

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and F unctions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 DC Characteristics: 24 V
    6. 7.6 DC Characteristics: 12 V
    7. 7.7 AC Characteristics: 24 V
    8. 7.8 AC Characteristics: 12 V
    9. 7.9 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 TPA3110D2 Modulation Scheme
        1. 9.3.1.1 Ferrite Bead Filter Considerations
        2. 9.3.1.2 Efficiency: LC Filter Required With The Traditional Class-D Modulation Scheme
        3. 9.3.1.3 When to Use an Output Filter for EMI Suppression
      2. 9.3.2 Gain Setting Via GAIN0 And GAIN1 Inputs
      3. 9.3.3 Differential Inputs
      4. 9.3.4 PLIMIT
      5. 9.3.5 GVDD Supply
      6. 9.3.6 PBTL Select
      7. 9.3.7 Thermal Protection
      8. 9.3.8 DC Detect
      9. 9.3.9 Short-Circuit Protection and Automatic Recovery Feature
    4. 9.4 Device Functional Modes
      1. 9.4.1 SD Operation
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Stereo Class-D Amplifier With BTL Output and Single-Ended Inputs With Power Limiting
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Input Resistance
          2. 10.2.1.2.2 Input Capacitor, CI
          3. 10.2.1.2.3 BSN and BSP Capacitors
          4. 10.2.1.2.4 Using Low-ESR Capacitors
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Stereo Class-D Amplifier With PBTL Output and Single-Ended Input
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curve
  11. 11Power Supply Recommendations
    1. 11.1 Power Supply Decoupling, CS
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Development Support
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Revision History

Changes from E Revision (November 2015) to F Revision

  • Added Measurement note added to characterization graphsGo
  • Added New Output Power vs Supply Voltage Characterization graphGo
  • Added footnote for heatsink and EVM Go

Changes from D Revision (July 2012) to E Revision

  • Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go

Changes from C Revision (August 2010) to D Revision

  • Added < 10 V/ms to VI in the Absolute Maximum Ratings table, added Note 2Go
  • Changed the PBTL Select section. Added text - "The voltage slew.......series with the terminals."Go
  • Added a 100kΩ resistor to AVCC Pin 14 and Note 1 to Figure 46Go

Changes from B Revision (July 2010) to C Revision

  • Replaced the Dissipations Ratings table with the Thermal Information tableGo

Changes from A Revision (July 2009) to B Revision

  • Added slew rate adjustment informationGo
  • Added AVCC to Pin 7 of Figure 46Go

Changes from * Revision (July 2009) to A Revision

  • Changed Changed the Stereo Class-D Amplifier with BTL Output and Single-Ended Input illustration Figure 42 - Corrected the pin names.Go
  • Changed Changed the Stereo Class-D Amplifier with PBTL Output and Single-Ended Input illustration Figure 46 - Corrected the pin names.Go