SLOS650F August   2009  – June 2016 TPA3113D2

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics, VCC = 24 V
    6. 6.6 DC Electrical Characteristics, VCC = 12 V
    7. 6.7 AC Electrical Characteristics, VCC = 24 V
    8. 6.8 AC Electrical Characteristics, VCC = 12 V
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Gain Setting Through GAIN0 and GAIN1 Inputs
      2. 7.3.2 SD Operation
      3. 7.3.3 PLIMIT
      4. 7.3.4 GVDD Supply
      5. 7.3.5 DC Detect
      6. 7.3.6 PBTL Select
      7. 7.3.7 Short-Circuit Protection and Automatic Recovery Feature
      8. 7.3.8 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 TPA3113D2 Modulation Scheme
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Stereo Class-D Amplifier With BTL Output
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Ferrite Bead Filter Considerations
          2. 8.2.1.2.2 Efficiency: LC Filter Required With the Traditional Class-D Modulation Scheme
          3. 8.2.1.2.3 When to Use an Output Filter for EMI Suppression
          4. 8.2.1.2.4 Input Resistance
          5. 8.2.1.2.5 Input Capacitor, CI
          6. 8.2.1.2.6 BSN and BSP Capacitors
          7. 8.2.1.2.7 Differential Inputs
          8. 8.2.1.2.8 Using LOW-ESR Capacitors
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Stereo Class-D Amplifier With BTL Output
      3. 8.2.3 Stereo Class-D Amplifier With PBTL Output
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply Decoupling, CS
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PCB Material Recommendation
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

PWP Package
28-Pin TSSOP
Top View

Pin Functions

PIN TYPE(1) DESCRIPTION
NO. NAME
1 SD I Shutdown logic input for audio amp (LOW = outputs Hi-Z, HIGH = outputs enabled). TTL logic levels with compliance to AVCC.
2 FAULT O Open drain output used to display short circuit or dc detect fault status. Voltage compliant to AVCC. Short circuit faults can be set to auto-recovery by connecting FAULT pin to SD pin. Otherwise, both short circuit faults and dc detect faults must be reset by cycling PVCC.
3 LINP I Positive audio input for left channel. Biased at 3 V.
4 LINN I Negative audio input for left channel. Biased at 3 V.
5 GAIN0 I Gain select least significant bit. TTL logic levels with compliance to AVCC.
6 GAIN1 I Gain select most significant bit. TTL logic levels with compliance to AVCC.
7 AVCC P Analog supply
8 AGND — Analog signal ground. Connect to the thermal pad.
9 GVDD O High-side FET gate drive supply. Nominal voltage is 7 V. Also should be used as supply for PLIMIT function
10 PLIMIT I Power limit level adjust. Connect a resistor divider from GVDD to GND to set power limit. Connect directly to GVDD for no power limit.
11 RINN I Negative audio input for right channel. Biased at 3 V.
12 RINP I Positive audio input for right channel. Biased at 3 V.
13 NC — Not connected
14 PBTL I Parallel BTL mode switch
15 PVCCR P Power supply for right channel H-bridge. Right channel and left channel power supply inputs are connect internally.
16 PVCCR P Power supply for right channel H-bridge. Right channel and left channel power supply inputs are connect internally.
17 BSPR I Bootstrap I/O for right channel, positive high-side FET.
18 OUTPR O Class-D H-bridge positive output for right channel.
19 PGND — Power ground for the H-bridges.
20 OUTNR O Class-D H-bridge negative output for right channel.
21 BSNR I Bootstrap I/O for right channel, negative high-side FET.
22 BSNL I Bootstrap I/O for left channel, negative high-side FET.
23 OUTNL O Class-D H-bridge negative output for left channel.
24 PGND — Power ground for the H-bridges.
25 OUTPL O Class-D H-bridge positive output for left channel.
26 BSPL I Bootstrap I/O for left channel, positive high-side FET.
27 PVCCL P Power supply for left channel H-bridge. Right channel and left channel power supply inputs are connect internally.
28 PVCCL P Power supply for left channel H-bridge. Right channel and left channel power supply inputs are connect internally.
29 PowerPAD — Connect to ground
(1) I = Input, O = Output, P = Power