SLOS862B July   2015  – October 2016 TPA3116D2-Q1 , TPA3118D2-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 AC Electrical Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Gain Setting and Master and Slave
      2. 7.3.2  Input Impedance
      3. 7.3.3  Start-Up and Shutdown Operation
      4. 7.3.4  PLIMIT Operation
      5. 7.3.5  GVDD Supply
      6. 7.3.6  BSPx and BSNx Capacitors
      7. 7.3.7  Differential Inputs
      8. 7.3.8  Device Protection System
      9. 7.3.9  DC-Detect Protection
      10. 7.3.10 Short-Circuit Protection and Automatic Recovery Feature
      11. 7.3.11 Thermal Protection
      12. 7.3.12 TPA311xD2-Q1 Modulation Scheme
        1. 7.3.12.1 MODSEL = GND: BD Modulation
        2. 7.3.12.2 MODSEL = HIGH: 1SPW Modulation
      13. 7.3.13 AM Avoidance EMI Reduction
    4. 7.4 Device Functional Mode
      1. 7.4.1 Mono Mode (PBTL)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Select the PWM Frequency
        2. 8.2.2.2 Select the Amplifier Gain and Master or Slave Mode
        3. 8.2.2.3 Select Input Capacitance
        4. 8.2.2.4 Select Decoupling Capacitors
        5. 8.2.2.5 Select Bootstrap Capacitors
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Heat Sink Used on the EVM
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Related Links
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Trademarks
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

This section describes a 2.1 master-and-slave application. The master is configured as stereo outputs and the slave is configured as a mono PBTL output.

8.2 Typical Application

A 2.1 solution, U1 TPA3116D2-Q1 in master mode 400 kHz, BTL, gain if 20 dB, power limit not implemented. U2 in Slave, PBTL mode gain of 20 dB. Inputs are connected for differential inputs.

TPA3116D2-Q1 TPA3118D2-Q1 typical_application3_SLOS862.gif Figure 19. Typical Application Schematic

8.2.1 Design Requirements

DESIGN PARAMETERS EXAMPLE VALUE
Input voltage range, V(PVCC) 4.5 V to 26 V
PWM output frequencies 400 kHz, 500 kHz, 600 kHz, 1 MHz or 1.2 MHz
Maximum output power 50 W

8.2.2 Detailed Design Procedure

The TPA311xD2-Q1 family is a very flexible and easy-to-use class-D amplifier; therefore, the design process is straightforward. Before beginning the design, gather the following information regarding the audio system.

  • PVCC rail planned for the design
  • Speaker or load impedance
  • Maximum output-power requirement
  • Desired PWM frequency

8.2.2.1 Select the PWM Frequency

Set the PWM frequency by using AM0, AM1 and AM2 pins.

8.2.2.2 Select the Amplifier Gain and Master or Slave Mode

In order to select the amplifier gain setting, the designer must determine the maximum power target and the speaker impedance. Once these parameters have been determined, calculate the required output-voltage swing which delivers the maximum output power.

Choose the lowest analog gain setting that produces an output-voltage swing greater than the required output swing for maximum power. The analog gain and master or slave mode can be set by selecting the voltage divider resistors (R1 and R2) on the GAIN/SLV pin.

8.2.2.3 Select Input Capacitance

Select the bulk capacitors at the PVCC inputs for proper voltage margin and adequate capacitance to support the power requirements. In practice, with a well-designed power supply, two 100-μF, 50-V capacitors should be sufficient. One capacitor should be placed near the PVCC inputs at each side of the device. PVCC capacitors should be a low-ESR type because they are being used in a high-speed switching application.

8.2.2.4 Select Decoupling Capacitors

Good-quality decoupling capacitors must be added at each of the PVCC inputs to provide good reliability, good audio performance, and to meet regulatory requirements. X5R or better ratings should be used in this application. Consider temperature, ripple current, and voltage overshoots when selecting decoupling capacitors. Also, these decoupling capacitors should be located near the PVCC and GND connections to the device in order to minimize series inductances.

8.2.2.5 Select Bootstrap Capacitors

Each of the outputs requires bootstrap capacitors to provide gate drive for the high-side output FETs. For this design, use 0.22-μF, 25-V capacitors of X5R quality or better.

8.2.3 Application Curves

TPA3116D2-Q1 TPA3118D2-Q1 D005_SLOS862.gif
Gain = 26 dB PVCC = 12 V TA = 25°C
RL = 4 Ω 10-µH + 0.68-µF filter
Figure 20. Total Harmonic Distortion + Noise (BTL) vs Output Power
TPA3116D2-Q1 TPA3118D2-Q1 D006_SLOS862.gif
Gain = 26 dB PVCC = 14.4 V TA = 25°C
RL = 4 Ω 10-µH + 0.68-µF filte
Figure 21. Total Harmonic Distortion + Noise (BTL) vs Output Power