SLOS862B July   2015  – October 2016 TPA3116D2-Q1 , TPA3118D2-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 AC Electrical Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Gain Setting and Master and Slave
      2. 7.3.2  Input Impedance
      3. 7.3.3  Start-Up and Shutdown Operation
      4. 7.3.4  PLIMIT Operation
      5. 7.3.5  GVDD Supply
      6. 7.3.6  BSPx and BSNx Capacitors
      7. 7.3.7  Differential Inputs
      8. 7.3.8  Device Protection System
      9. 7.3.9  DC-Detect Protection
      10. 7.3.10 Short-Circuit Protection and Automatic Recovery Feature
      11. 7.3.11 Thermal Protection
      12. 7.3.12 TPA311xD2-Q1 Modulation Scheme
        1. 7.3.12.1 MODSEL = GND: BD Modulation
        2. 7.3.12.2 MODSEL = HIGH: 1SPW Modulation
      13. 7.3.13 AM Avoidance EMI Reduction
    4. 7.4 Device Functional Mode
      1. 7.4.1 Mono Mode (PBTL)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Select the PWM Frequency
        2. 8.2.2.2 Select the Amplifier Gain and Master or Slave Mode
        3. 8.2.2.3 Select Input Capacitance
        4. 8.2.2.4 Select Decoupling Capacitors
        5. 8.2.2.5 Select Bootstrap Capacitors
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Heat Sink Used on the EVM
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Related Links
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Trademarks
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

DAD PowerPAD™ Package
32-Pin HTSSOP With Exposed Thermal Pad Up
TPA3116D2-Q1 Top View
DAP PowerPAD™ Package
32-Pin HTSSOP With Exposed Thermal Pad Down
TPA3118D2-Q1 Top View

Pin Functions

PIN TYPE(1) DESCRIPTION
NAME NO.
AM[2:0] 13–15 I AM avoidance frequency selection
AVCC 17 P Analog supply
BSNL 20 BST Bootstrap for negative left channel output, connect to 220-nF X5R, or better ceramic cap to OUTPL
BSNR 26 BST Bootstrap for negative right channel output, connect to 220-nF X5R, or better ceramic cap to OUTNR
BSPL 24 BST Bootstrap for positive left channel output, connect to 220-nF X5R, or better ceramic cap to OUTNL
BSPR 30 BST Bootstrap for positive right channel output, connect to 220-nF X5R or better ceramic cap to OUTPR
FAULT 3 DO General fault reporting including overtemperature, dc detect, open drain.
FAULT = High, normal operation
FAULT = Low, fault condition
GAIN/SLV 8 I Selects gain and selects between master and slave modes depending on pin voltage divider.
GND 9, 22, 25, 28 G Ground
GVDD 7 PO Internally generated gate voltage supply. Not to be used as a supply or connected to any component other than a 1-µF X7R ceramic decoupling capacitor and the PLIMIT and GAIN/SLV resistor dividers.
LINN 11 I Negative audio input for left channel. Biased at 3 V. Connect to GND for PBTL mode.
LINP 10 I Positive audio input for left channel. Biased at 3 V. Connect to GND for PBTL mode.
MODSEL 1 I Mode selection logic input (LOW = BD mode, HIGH = 1 SPW mode). TTL logic levels with compliance to AVCC.
MUTE 12 I Mute signal for fast disable or enable of outputs (HIGH = outputs Hi-Z, LOW = outputs enabled). TTL logic levels with compliance to AVCC.
OUTNL 21 PO Negative left-channel output
OUTNR 27 PO Negative right-channel output
OUTPL 23 PO Positive left-channel output
OUTPR 29 PO Positive right-channel output
PLIMIT 6 I Power limit level adjust. Connect a resistor divider from GVDD to GND to set power limit. Connect directly to GVDD for no power limit.
PVCC 18, 19, 31, 32 P Power supply
RINN 5 I Negative audio input for right channel. Biased at 3 V.
RINP 4 I Positive audio input for right channel. Biased at 3 V.
SD 2 I Shutdown logic input for audio amp (LOW = outputs Hi-Z, HIGH = outputs enabled). TTL logic levels with compliance to AVCC.
SYNC 16 DIO Clock input/output for synchronizing multiple class-D devices. Direction determined by GAIN/SLV pin.
Thermal pad — G Connect to GND for best system performance. If not connected to GND, leave floating.
(1) TYPE: DO = Digital output, I = Analog input, G = General ground, PO = Power output, BST = Bootstrap.