SLOS862B July 2015 – October 2016 TPA3116D2-Q1 , TPA3118D2-Q1
PRODUCTION DATA.
The TPA311xD2-Q1 devices are automotive stereo, efficient, digital-amplifier power stages for driving speakers up to 100 W into 2 Ω in mono. The TPA3118D2-Q1 can even drive 2 × 30 W into 8 Ω without a heat sink on a dual-layer PCB. If even higher power is needed, the TPA3116D2-Q1 drives 2 × 50 W into 4 Ω with a small heat sink attached to its top-side thermal pad.
The TPA311xD2-Q1 advanced oscillator and PLL circuit employ a multiple-switching-frequency option to avoid AM interference; this is achieved together with an option of either master or slave selection, making it possible to synchronize multiple devices.
The TPA311xD2-Q1 devices are fully protected against faults with short-circuit protection and thermal protection as well as overvoltage, undervoltage and dc protection. Faults are reported back to the processor to prevent devices from being damaged during overload conditions.
DEVICE | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPA3116D2-Q1 | HTSSOP (32) | 11.00 mm × 6.20 mm |
TPA3118D2-Q1 |
Changes from A Revision (August 2015) to B Revision
Changes from * Revision (July 2015) to A Revision
PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
AM[2:0] | 13–15 | I | AM avoidance frequency selection |
AVCC | 17 | P | Analog supply |
BSNL | 20 | BST | Bootstrap for negative left channel output, connect to 220-nF X5R, or better ceramic cap to OUTPL |
BSNR | 26 | BST | Bootstrap for negative right channel output, connect to 220-nF X5R, or better ceramic cap to OUTNR |
BSPL | 24 | BST | Bootstrap for positive left channel output, connect to 220-nF X5R, or better ceramic cap to OUTNL |
BSPR | 30 | BST | Bootstrap for positive right channel output, connect to 220-nF X5R or better ceramic cap to OUTPR |
FAULT | 3 | DO | General fault reporting including overtemperature, dc detect, open drain. FAULT = High, normal operation FAULT = Low, fault condition |
GAIN/SLV | 8 | I | Selects gain and selects between master and slave modes depending on pin voltage divider. |
GND | 9, 22, 25, 28 | G | Ground |
GVDD | 7 | PO | Internally generated gate voltage supply. Not to be used as a supply or connected to any component other than a 1-µF X7R ceramic decoupling capacitor and the PLIMIT and GAIN/SLV resistor dividers. |
LINN | 11 | I | Negative audio input for left channel. Biased at 3 V. Connect to GND for PBTL mode. |
LINP | 10 | I | Positive audio input for left channel. Biased at 3 V. Connect to GND for PBTL mode. |
MODSEL | 1 | I | Mode selection logic input (LOW = BD mode, HIGH = 1 SPW mode). TTL logic levels with compliance to AVCC. |
MUTE | 12 | I | Mute signal for fast disable or enable of outputs (HIGH = outputs Hi-Z, LOW = outputs enabled). TTL logic levels with compliance to AVCC. |
OUTNL | 21 | PO | Negative left-channel output |
OUTNR | 27 | PO | Negative right-channel output |
OUTPL | 23 | PO | Positive left-channel output |
OUTPR | 29 | PO | Positive right-channel output |
PLIMIT | 6 | I | Power limit level adjust. Connect a resistor divider from GVDD to GND to set power limit. Connect directly to GVDD for no power limit. |
PVCC | 18, 19, 31, 32 | P | Power supply |
RINN | 5 | I | Negative audio input for right channel. Biased at 3 V. |
RINP | 4 | I | Positive audio input for right channel. Biased at 3 V. |
SD | 2 | I | Shutdown logic input for audio amp (LOW = outputs Hi-Z, HIGH = outputs enabled). TTL logic levels with compliance to AVCC. |
SYNC | 16 | DIO | Clock input/output for synchronizing multiple class-D devices. Direction determined by GAIN/SLV pin. |
Thermal pad | — | G | Connect to GND for best system performance. If not connected to GND, leave floating. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply voltage, VCC | PVCC, AVCC | –0.3 | 30 | V |
Input voltage, VI | INPL, INNL, INPR, INNR | –0.3 | 6.3 | V |
PLIMIT, GAIN/SLV, SYNC | –0.3 | GVDD + 0.3 | V | |
AM0, AM1, AM2, MUTE, SD, MODSEL | –0.3 | PVCC + 0.3 | V | |
Slew rate, maximum(2) | AM0, AM1, AM2, MUTE, SD, MODSEL | 10 | V/ms | |
Operating ambient temperature, TA | –40 | 125 | °C | |
Operating junction temperature range, TJ | –40 | 150 | °C | |
Storage temperature range, Tstg | –40 | 125 | °C |
VALUE | UNIT | ||||
---|---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per AEC Q100-002(1) | ±2000 | V | |
Charged-device model (CDM), per AEC Q100-011 | All pins | ±450 | |||
Corner pins (1, 16, 17, and 32) | ±450 |
MIN | NOM | MAX | UNIT | ||||
---|---|---|---|---|---|---|---|
VCC | Supply voltage | PVCC, AVCC | 4.5 | 26 | V | ||
VIH | High-level input voltage | AM0, AM1, AM2, MUTE, SD, SYNC, MODSEL | 2 | V | |||
VIL | Low-level input voltage | AM0, AM1, AM2, MUTE, SD, SYNC, MODSEL | 0.8 | V | |||
VOL | Low-level output voltage | FAULT, RPULLUP = 100 kΩ, V(PVCC) = 26 V | 0.8 | V | |||
IIH | High-level input current | AM0, AM1, AM2, MUTE, SD, MODSEL (VI = 2 V, VCC = 18 V) | 50 | µA | |||
RL | Minimum load impedance | Output filter: L = 10 µH, C = 680 nF, BTL | 3.2 | 4 | Ω | ||
Output filter: L = 10 µH, C = 1 µF, PBTL | 1.6 | ||||||
Lo | Output-filter inductance | Minimum output filter inductance under short-circuit condition | 1 | µH |
THERMAL METRIC(1) | TPA3116D2-Q1 | TPA3118D2-Q1 | UNIT | |
---|---|---|---|---|
DAD | DAP | |||
32 PINS | 32 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 44.7(2) | 32.4 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 1.2 | 17.2 | °C/W |
RθJB | Junction-to-board thermal resistance | 21.5 | 17.3 | °C/W |
ψJT | Junction-to-top characterization parameter | 1.2 | 0.4 | °C/W |
ψJB | Junction-to-board characterization parameter | 21 | 17.2 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | N/A | 1 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
| VOS | | Class-D output offset voltage (measured differentially) | VI = 0 V, gain = 36 dB | 1.5 | 15 | mV | ||
ICC | Quiescent supply current | SD = 2 V, no load or filter, V(PVCC) = 12 V | 20 | 35 | mA | ||
SD = 2 V, no load or filter, V(PVCC) = 24 V | 32 | 50 | |||||
ICC(SD) | Quiescent supply current in shutdown mode | SD = 0.8 V, no load or filter, V(PVCC) = 12 V | <50 | µA | |||
SD = 0.8 V, no load or filter, V(PVCC) = 24 V | 50 | 400 | |||||
rDS(on) | Drain-source on-state resistance, measured pin-to-pin | V(PVCC) = 21 V, IO = 500 mA, TJ = 25°C | 120 | mΩ | |||
G | Gain (BTL) | R1 = open, R2 = 20 kΩ | 19 | 20 | 21 | dB | |
R1 = 100 kΩ, R2 = 20 kΩ | 25 | 26 | 27 | ||||
R1 = 100 kΩ, R2 = 39 kΩ | 31 | 32 | 33 | dB | |||
R1 = 75 kΩ, R2 = 47 kΩ | 35 | 36 | 37 | ||||
G | Gain (SLV) | R1 = 51 kΩ, R2 = 51 kΩ | 19 | 20 | 21 | dB | |
R1 = 47 kΩ, R2 = 75 kΩ | 25 | 26 | 27 | ||||
R1 = 39 kΩ, R2 = 100 kΩ | 31 | 32 | 33 | dB | |||
R1 = 16 kΩ, R2 = 100 kΩ | 35 | 36 | 37 | ||||
ton | Turn-on time | V(SD) = 2 V | 10 | ms | |||
toff | Turn-off time | V(SD) = 0.8 V | 2 | µs | |||
GVDD | Gate drive supply | I(GVDD) < 200 µA | 6.4 | 6.9 | 7.4 | V | |
VO | Output voltage maximum under PLIMIT control | V(PLIMIT) = 2 V; VI = 1 Vrms | 6.75 | 7.9 | 8.75 | V |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
KSVR | Power supply ripple rejection | 200 mVPP ripple at 1 kHz, gain = 20 dB, inputs ac-coupled to GND | –70 | dB | ||
PO | Continuous output power | THD+N = 10%, f = 1 kHz, V(PVCC) = 14.4 V | 25 | W | ||
THD+N = 10%, f = 1 kHz, V(PVCC) = 21 V | 50 | |||||
THD+N | Total harmonic distortion + noise | VCC = 21 V, f = 1 kHz, PO = 25 W (half-power) | 0.1% | |||
Vn | Output integrated noise | 20 Hz to 22 kHz, A-weighted filter, gain = 20 dB | 65 | µV | ||
–80 | dBV | |||||
Crosstalk | VO = 1 Vrms, gain = 20 dB, f = 1 kHz | –100 | dB | |||
SNR | Signal-to-noise ratio | Maximum output at THD+N < 1%, f = 1 kHz, gain = 20 dB, A-weighted | 102 | dB | ||
fOSC | Oscillator frequency | AM[2:0] = 000 | 376 | 400 | 424 | kHz |
AM[2:0] = 001 | 470 | 500 | 530 | |||
AM[2:0] = 010 | 564 | 600 | 636 | |||
AM[2:0] = 011 | 940 | 1000 | 1060 | |||
AM[2:0] = 100 | 1128 | 1200 | 1278 | |||
AM[2:0] = 101 | Reserved | |||||
AM[2:0] = 110 | ||||||
AM[2:0] = 111 | ||||||
Thermal trip point | 150 | °C | ||||
Thermal hysteresis | 15 | °C | ||||
Overcurrent trip point | 7.5 | A |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
td | Delay from MUTE rising to SD falling | 1.4 | s |
Gain = 26 dB | PVCC = 6 V | TA = 25°C |
RL = 4 Ω | 10-µH + 0.68-µF filter |
Gain = 26 dB | PVCC = 6 V | TA = 25°C |
RL = 4 Ω | 10-µH + 0.68-µF filter |
Gain = 26 dB | PVCC = 14.4 V | TA = 25°C |
RL = 4 Ω | 10-µH + 0.68-µF filter |
Gain = 26 dB | TA = 25°C | RL = 4 Ω |
10-µH + 0.68-µF filter |
Gain = 26 dB | PVCC = 14.4 V | TA = 25°C |
RL = 4 Ω | 22-µH + 1-µF filter |
Gain = 26 dB | PVCC = 14.4 V | TA = 25°C |
RL = 4 Ω | 10-µH + 0.68-µF filter |
Gain = 26 dB | PVCC = 14.4 V | TA = 25°C |
RL = 4 Ω | 10-µH + 0.68-µF filter |
Gain = 26 dB | TA = 25°C | RL = 4 Ω |
10-µH + 0.68-µF filter |
Gain = 26 dB | PVCC = 12 V | TA = 25°C |
RL = 4 Ω | 10-µH + 0.68-µF filter |
PVCC = 14.4 V | TA = 25°C | RL = 4 Ω |
22-µH + 3.3-µF filter |
The TPA311xD2-Q1 devices are highly efficient class-D audio amplifiers with integrated 120-mΩ MOSFETs that allow output currents up to 7.5 A. The high efficiency allows the amplifier to provide an excellent audio performance without the need for a bulky heat sink.
The device can be configured for either master or slave operation by using the SYNC pin. Doing so helps to prevent audible beat noise.
The gain of the TPA311xD2-Q1 family is set by the voltage divider connected to the GAIN/SLV control pin. Master or slave mode is also controlled by the same pin. An internal ADC is used to detect the eight input states. The first four stages set the GAIN in master mode to gains of 20, 26, 32, and 36 dB, respectively, whereas the next four stages set the GAIN in slave mode to gains of 20, 26, 32, and 36 dB, respectively. The gain setting is latched during power up and cannot be changed while device is powered. Table 1 lists the recommended resistor values and the state and gain.
MASTER / SLAVE MODE | GAIN | R1 (to GND)(1) | R2 (to GVDD)(1) | INPUT IMPEDANCE |
---|---|---|---|---|
Master | 20 dB | 5.6 kΩ | OPEN | 60 kΩ |
Master | 26 dB | 20 kΩ | 100 kΩ | 30 kΩ |
Master | 32 dB | 39 kΩ | 100 kΩ | 15 kΩ |
Master | 36 dB | 47 kΩ | 75 kΩ | 9 kΩ |
Slave | 20 dB | 51 kΩ | 51 kΩ | 60 kΩ |
Slave | 26 dB | 75 kΩ | 47 kΩ | 30 kΩ |
Slave | 32 dB | 100 kΩ | 39 kΩ | 15 kΩ |
Slave | 36 dB | 100 kΩ | 16 kΩ | 9 kΩ |
In master mode, the SYNC terminal is an output, in slave mode, SYNC terminal is an input for a clock input.
The input stage of the TPA311xD2-Q1 family is a fully differential input stage, and the input impedance changes with the gain setting from 9 kΩ at 36-dB gain to 60 kΩ at 20-dB gain. Table 1 lists the values from mininimum to maximum gain. The tolerance of the input resistor value is ±20%, so the minimum value is higher than 7.2 kΩ. The inputs must be ac-coupled to minimize the output dc offset and ensure correct ramping of the output voltages during power ON and power OFF. The input ac-coupling capacitor together with the input impedance forms a high-pass filter with the following cutoff frequency:
If a flat bass response is required down to 20 Hz, the recommended cutoff frequency is a tenth of that, 2 Hz. Table 2 lists the recommended ac-coupling capacitors for each gain step. If –3 dB is accepted at 20 Hz, 10 times lower capacitors can used – for example, a 1 µF can be used.
GAIN | INPUT IMPEDANCE | INPUT CAPACITANCE | HIGH-PASS FILTER |
---|---|---|---|
20 dB | 60 kΩ | 1.5 µF | 1.8 Hz |
26 dB | 30 kΩ | 3.3 µF | 1.6 Hz |
32 dB | 15 kΩ | 5.6 µF | 2.3 Hz |
36 dB | 9 kΩ | 10 µF | 1.8 Hz |
The input capacitors used should be a type with low leakage, like quality electrolytic, tantalum, or ceramic. If a polarized type is used, the positive connection should face the input pins, which are biased to 3 Vdc.
The TPA311xD2-Q1 family employs a shutdown mode of operation designed to reduce supply current (ICC) to the absolute minimum level for power conservation during periods of nonuse. The SD input pin should be held high (see Recommended Operating Conditions for SD VIH and VIL levels) during normal operation when the amplifier is in use. Pulling SD low sets the outputs to mute, and the amplifier enters a low-current state. It is not recommended to leave SD unconnected, because amplifier operation would be unpredictable.
For the best power-off pop performance, place the amplifier in the shutdown mode prior to removing the power supply. The gain setting is selected at the end of the start-up cycle. At the end of the start-up cycle, the gain is selected and cannot be changed until the next power up.
The TPA311xD2-Q1 family has a built-in voltage limiter that can be used to limit the output voltage level below the supply rail, the amplifier simply operates as if it was powered by a lower supply voltage, and thereby limits the output power. Add a resistor divider from GVDD to ground to set the voltage at the PLIMIT pin. An external reference may also be used if tighter tolerance is required. Add a 1-µF capacitor from the PLIMIT pin to ground to ensure stability. It is recommended to connect PLIMIT to GVDD when using 1SPW-modulation mode.
The PLIMIT circuit sets a limit on the output peak-to-peak voltage. The limiting is done by limiting the duty cycle to a fixed maximum value. This limit can be thought of as a virtual voltage rail which is lower than the supply connected to PVCC. This virtual rail is approximately 4 times the voltage at the PLIMIT pin. This output voltage can be used to calculate the maximum output power for a given maximum input voltage and speaker impedance.
where
PVCC (V) | PLIMIT VOLTAGE (V)(1) | R to GND | R to GVDD | OUTPUT VOLTAGE (Vrms) |
---|---|---|---|---|
24 V | GVDD | Open | Short | 17.9 |
24 V | 3.3 | 45 kΩ | 51 kΩ | 12.67 |
24 V | 2.25 | 24 kΩ | 51 kΩ | 9 |
12 V | GVDD | Open | Short | 10.33 |
12 V | 2.25 | 24 kΩ | 51 kΩ | 9 |
12 V | 1.5 | 18 kΩ | 68 kΩ | 6.3 |
The GVDD supply is used to power the gates of the output full-bridge transistors. The GVDD supply can also be used to supply the PLIMIT and GAIN/SLV voltage dividers. Decouple GVDD with an X5R ceramic 1-µF capacitor to GND. The GVDD supply is not intended to be used for external supply. It is recommended to limit the current consumption by using resistor voltage dividers of 100 kΩ or more for GAIN/SLV and PLIMIT.
The full H-bridge output stages use only NMOS transistors. Therefore, to turn on correctly they require bootstrap capacitors for the high side of each output. A 220-nF ceramic capacitor of quality X5R or better, rated for at least 16 V, must be connected from each output to its corresponding bootstrap input. (See the application circuit diagram in Figure 19.) The bootstrap capacitors connected between the BSxx pins and their corresponding outputs function as a floating power supply for the high-side N-channel power MOSFET gate-drive circuitry. During each high-side switching cycle, the bootstrap capacitors hold the gate-to-source voltage high enough to keep the high-side MOSFETs turned on.
The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel. To use the TPA311xD2-Q1 family with a differential source, connect the positive lead of the audio source to the RINP or LINP input and the negative lead from the audio source to the RINN or LINN input. To use the TPA311xD2-Q1 family with a single-ended source, ac-ground the negative input through a capacitor equal in value to the input capacitor on the positive input and apply the audio source to either input. In a single-ended input application, the unused input should be ac-grounded at the audio source instead of at the device input for best noise performance. For good transient performance, the impedance seen at each of the two differential inputs should be the same.
The impedance seen at the inputs should be limited to an RC time constant of 1 ms or less if possible. This is to allow the input dc-blocking capacitors to become completely charged during the 10-ms power-up time. If the input capacitors are not allowed to completely charge, there is some additional sensitivity to component matching which can result in a pop if the input components are not well matched.
The TPA311xD2-Q1 family contains a complete set of protection circuits to make system design efficient as well as to protect the device against any kind of permanent failures due to short circuits, overload, overtemperature, and undervoltage. The FAULT pin signals if an error is detected according to Table 4:
FAULT | TRIGGERING CONDITION (typical value) |
FAULT | ACTION | LATCHED OR SELF-CLEARING |
---|---|---|---|---|
Overcurrent | Output short or short to PVCC or GND | Low | Output high impedance | Latched |
Overtemperature | Tj > 150°C | Low | Output high impedance | Latched |
Too-high dc offset | DC output voltage | Low | Output high impedance | Latched |
Undervoltage on PVCC | V(PVCC) < 4.5 V | – | Output high impedance | Self-clearing |
Overvoltage on PVCC | V(PVCC) > 27 V | – | Output high impedance | Self-clearing |
The TPA311xD2-Q1 family has circuitry which protects the speakers from dc current, which might occur due to defective capacitors on the input or shorts on the printed circuit board at the inputs. A dc-detect fault is reported on the FAULT pin as a low state. The dc-detect fault also causes the amplifier to shut down by changing the state of the outputs to Hi-Z.
If automatic recovery from the short-circuit protection latch is desired, connect the FAULT pin directly to the SD pin. This allows the FAULT pin function to automatically drive the SD pin low which clears the dc-detect protection latch.
A dc-detect fault is issued when the output differential duty-cycle of either channel exceeds 60% for more than 420 ms at the same polarity. For several values of the supply voltage, Table 5 shows some examples of the typical output offset voltages that trigger dc-detect protection. This feature protects the speaker from large dc currents or ac currents less than 2 Hz. To avoid nuisance faults due to the dc-detect circuit, hold the SD pin low at power up until the signals at the inputs are stable. Also, take care to match the impedance seen at the positive and negative inputs to avoid nuisance dc-detect faults.
Table 5 lists the minimum output offset voltages required to trigger the dc detect. The outputs must remain at or above the voltage listed in the table for more than 420 ms to trigger the dc detect.
V(PVCC) (V) | VOS - OUTPUT OFFSET VOLTAGE (V) |
---|---|
4.5 | 0.96 |
6 | 1.3 |
12 | 2.6 |
18 | 3.9 |
The TPA311xD2-Q1 family has protection from overcurrent conditions caused by a short circuit on the output stage. The short-circuit protection fault is reported on the FAULT pin as a low state. The amplifier outputs are switched to a high-impedance state when the short-circuit protection latch is engaged. The latch can be cleared by cycling the SD pin through the low state.
If automatic recovery from the short-circuit protection latch is desired, connect the FAULT pin directly to the SD pin. This allows the FAULT pin function to automatically drive the SD pin low, which clears the short-circuit protection latch.
In systems where a possibility of a permanent short from the output to PVDD or to a high-voltage battery like a car battery can occur, pull the MUTE pin low with the FAULT signal and an inverting transistor to ensure a high-Z restart, as shown in Figure 15.
Thermal protection on the TPA311xD2-Q1 family prevents damage to the device when the internal die temperature exceeds 150°C. There is a ±15°C tolerance on this trip point from device to device. Once the die temperature exceeds the thermal trip point, the device enters the shutdown state and the outputs are disabled. This is a latched fault.
Thermal protection faults are reported on the FAULT pin as a low state.
If automatic recovery from the thermal protection latch is desired, connect the FAULT pin directly to the SD pin. This allows the FAULT pin function to automatically drive the SD pin low, which clears the thermal protection latch.
The TPA311xD2-Q1 family has the option of running in either BD modulation or 1SPW modulation; this is set by the MODSEL pin.
Each output is switching from 0 volts to the supply voltage. The OUTPx and OUTNx are in phase with each other with no input so that there is little or no current in the speaker. The duty cycle of OUTPx is greater than 50% and OUTNx is less than 50% for positive output voltages. The duty cycle of OUTPx is less than 50% and OUTNx is greater than 50% for negative output voltages. The voltage across the load sits at 0 V throughout most of the switching period, reducing the switching current, which reduces any I2R losses in the load.
The 1SPW mode alters the normal modulation scheme in order to achieve higher efficiency with a slight penalty in THD degradation, and more attention required in the output filter selection. In 1SPW mode, the outputs operate at approximately 15% modulation during idle conditions. When an audio signal is applied, one output decreases and one increases. The decreasing output signal quickly rails to GND at which point all the audio modulation takes place through the rising output. The result is that only one output is switching during a majority of the audio cycle. Efficiency is improved in this mode due to the reduction of switching losses. The THD penalty in 1SPW mode is minimized by the high-performance feedback loop. The resulting audio signal at each half-output has a discontinuity each time the output rails to GND. This can cause ringing in the audio reconstruction filter unless care is taken in the selection of the filter components and type of filter used.
To reduce interference in the AM radio band, the TPA3116D2-Q1 has the ability to change the switching frequency via the AM[2:0] pins. The recommended frequencies are listed in Table 6. The fundamental frequency and its second harmonic straddle the AM radio band listed. This eliminates the tones that can be present due to the switching frequency being demodulated by the AM radio.
US | EUROPEAN | ||||
---|---|---|---|---|---|
AM FREQUENCY (kHz) | AM FREQUENCY (kHz) | SWITCHING FREQUENCY (kHz) | AM2 | AM1 | AM0 |
522–540 | |||||
540–917 | 540–914 | 500 | 0 | 0 | 1 |
917–1125 | 914–1122 | 600 (or 400) | 0 | 1 | 0 |
0 | 0 | 0 | |||
1125–1375 | 1122–1373 | 500 | 0 | 0 | 1 |
1375–1547 | 1373–1548 | 600 (or 400) | 0 | 1 | 0 |
0 | 0 | 0 | |||
1547–1700 | 1548–1701 | 600 (or 500) | 0 | 1 | 0 |
0 | 0 | 1 |
The TPA311xD2-Q1 family can be connected in MONO mode enabling up to 100-W output power. This is done by:
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
This section describes a 2.1 master-and-slave application. The master is configured as stereo outputs and the slave is configured as a mono PBTL output.
A 2.1 solution, U1 TPA3116D2-Q1 in master mode 400 kHz, BTL, gain if 20 dB, power limit not implemented. U2 in Slave, PBTL mode gain of 20 dB. Inputs are connected for differential inputs.
DESIGN PARAMETERS | EXAMPLE VALUE |
---|---|
Input voltage range, V(PVCC) | 4.5 V to 26 V |
PWM output frequencies | 400 kHz, 500 kHz, 600 kHz, 1 MHz or 1.2 MHz |
Maximum output power | 50 W |
The TPA311xD2-Q1 family is a very flexible and easy-to-use class-D amplifier; therefore, the design process is straightforward. Before beginning the design, gather the following information regarding the audio system.
Set the PWM frequency by using AM0, AM1 and AM2 pins.
In order to select the amplifier gain setting, the designer must determine the maximum power target and the speaker impedance. Once these parameters have been determined, calculate the required output-voltage swing which delivers the maximum output power.
Choose the lowest analog gain setting that produces an output-voltage swing greater than the required output swing for maximum power. The analog gain and master or slave mode can be set by selecting the voltage divider resistors (R1 and R2) on the GAIN/SLV pin.
Select the bulk capacitors at the PVCC inputs for proper voltage margin and adequate capacitance to support the power requirements. In practice, with a well-designed power supply, two 100-μF, 50-V capacitors should be sufficient. One capacitor should be placed near the PVCC inputs at each side of the device. PVCC capacitors should be a low-ESR type because they are being used in a high-speed switching application.
Good-quality decoupling capacitors must be added at each of the PVCC inputs to provide good reliability, good audio performance, and to meet regulatory requirements. X5R or better ratings should be used in this application. Consider temperature, ripple current, and voltage overshoots when selecting decoupling capacitors. Also, these decoupling capacitors should be located near the PVCC and GND connections to the device in order to minimize series inductances.
Each of the outputs requires bootstrap capacitors to provide gate drive for the high-side output FETs. For this design, use 0.22-μF, 25-V capacitors of X5R quality or better.
Gain = 26 dB | PVCC = 12 V | TA = 25°C |
RL = 4 Ω | 10-µH + 0.68-µF filter |
Gain = 26 dB | PVCC = 14.4 V | TA = 25°C |
RL = 4 Ω | 10-µH + 0.68-µF filte |
The power supply requirements for the TPA3116D2-Q1 consist of one higher-voltage supply to power the output stage of the speaker amplifier. Several on-chip regulators are included on the TPA3116D2-Q1 to generate the voltages necessary for the internal circuitry of the audio path. It is important to note that the voltage regulators which have been integrated are sized only to provide the current necessary to power the internal circuitry. The external pins are provided only as a connection point for off-chip bypass capacitors to filter the supply. Connecting external circuitry to these regulator outputs may result in reduced performance and damage to the device. The high-voltage supply, between 4.5 V and 26 V, supplies the analog circuitry (AVCC) and the power stage (PVCC). The AVCC supply feeds the internal LDOs, including GVDD. The LDO outputs are connected to external pins for filtering purposes, but should not be connected to external circuits. The GVDD LDO output has been sized to provide current necessary for internal functions but not for external loading.
Because the class-D switching edges are fast, it is necessary to take care when planning the layout of the printed circuit board. The following suggestions help to meet EMC requirements.
For an example layout, see the TPA3116D2 Evaluation Module (TPA3116D2EVM) User Guide (SLOU336). Both the EVM user manual and the thermal pad application reports, SLMA002 and SLMA004, are available on the TI Web site at http://www.ti.com.
The heat sink (part number ATS-TI 10 OP-521-C1-R1 or equivalent) used on the EVM is a 14-mm × 25-mm × 50-mm extruded aluminum heat sink with three fins (see Figure 24). For additional information on the heat sink, go to www.qats.com.
This size heat sink has shown to be sufficient for continuous output power. The crest factor of music and having airflow lowers the requirement for heat sinking, and smaller types of heat sinks can be used.
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The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy.
PARTS | PRODUCT FOLDER | SAMPLE & BUY | TECHNICAL DOCUMENTS | TOOLS & SOFTWARE | SUPPORT & COMMUNITY |
---|---|---|---|---|---|
TPA3116D2-Q1 | Click here | Click here | Click here | Click here | Click here |
TPA3118D2-Q1 | Click here | Click here | Click here | Click here | Click here |
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The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
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SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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