SLOS942 April   2018 TPA3126D2

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      TPA3126 and TPA3116 Idle Current
      2.      Simplified Application Circuit
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 DC Electrical Characteristics
    6. 7.6 AC Electrical Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Gain Setting and Master and Slave
      2. 8.3.2  Input Impedance
      3. 8.3.3  Startup and Shutdown Operation
      4. 8.3.4  PLIMIT Operation
      5. 8.3.5  GVDD Supply
      6. 8.3.6  BSPx and BSNx Capacitors
      7. 8.3.7  Differential Inputs
      8. 8.3.8  Device Protection System
      9. 8.3.9  DC Detect Protection
      10. 8.3.10 Short-Circuit Protection and Automatic Recovery Feature
      11. 8.3.11 Thermal Protection
      12. 8.3.12 Device Modulation Scheme
        1. 8.3.12.1 BD Modulation
      13. 8.3.13 Efficiency: LC Filter Required with the Traditional Class-D Modulation Scheme
      14. 8.3.14 Ferrite Bead Filter Considerations
      15. 8.3.15 When to Use an Output Filter for EMI Suppression
      16. 8.3.16 AM Avoidance EMI Reduction
    4. 8.4 Device Functional Modes
      1. 8.4.1 Mono PBTL Mode
      2. 8.4.2 Mono BTL Mode (Single Channel Mode)
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Typical Application
        1. 9.1.1.1 Design Requirements
        2. 9.1.1.2 Detailed Design Procedure
          1. 9.1.1.2.1 Select the PWM Frequency
          2. 9.1.1.2.2 Select the Amplifier Gain and Master/Slave Mode
          3. 9.1.1.2.3 Select Input Capacitance
          4. 9.1.1.2.4 Select Decoupling Capacitors
          5. 9.1.1.2.5 Select Bootstrap Capacitors
        3. 9.1.1.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Mode
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Heat Sink Used on the EVM
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Related Documentation
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.9 DC Detect Protection

The TPA3126D2 has circuitry which protects the speakers from DC current which might occur due to defective capacitors on the input or shorts on the printed circuit board at the inputs. A DC detect fault is reported on the FAULT pin as a low state. The DC Detect fault causes the amplifier to shutdown by changing the state of the outputs to Hi-Z.

If automatic recovery from the short circuit protection latch is desired, connect the FAULTZ pin directly to the SDZ pin. Connecting the FAULTZ and SDZ pins allows the FAULTZ pin function to automatically drive the SDZ pin low which clears the DC Detect protection latch.

A DC Detect Fault is issued when the output differential voltage of either channel exceeds DC protection threshold level for more than 640 ms at the same polarity. Table 5 shows some examples of the typical DC Detect Protection threshold for several values of the supply voltage. The Detect Protection Threshold feature protects the speaker from large DC currents or AC currents less than 2 Hz. To avoid nuisance faults due to the DC detect circuit, hold the SD pin low at power-up until the signals at the inputs are stable. Also, take care to match the impedance seen at the positive and negative inputs to avoid nuisance DC detect faults.

Table 5 lists the minimum output offset voltages required to trigger the DC detect. The outputs must remain at or above the voltage listed in the table for more than 640 ms to trigger the DC detect.

Table 5. DC Detect Threshold

PVCC (V) VOS - OUTPUT OFFSET VOLTAGE (V)
4.5 1.35
6 1.8
12 3.6
18 5.4