SLOS942 April   2018 TPA3126D2

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      TPA3126 and TPA3116 Idle Current
      2.      Simplified Application Circuit
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 DC Electrical Characteristics
    6. 7.6 AC Electrical Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Gain Setting and Master and Slave
      2. 8.3.2  Input Impedance
      3. 8.3.3  Startup and Shutdown Operation
      4. 8.3.4  PLIMIT Operation
      5. 8.3.5  GVDD Supply
      6. 8.3.6  BSPx and BSNx Capacitors
      7. 8.3.7  Differential Inputs
      8. 8.3.8  Device Protection System
      9. 8.3.9  DC Detect Protection
      10. 8.3.10 Short-Circuit Protection and Automatic Recovery Feature
      11. 8.3.11 Thermal Protection
      12. 8.3.12 Device Modulation Scheme
        1. 8.3.12.1 BD Modulation
      13. 8.3.13 Efficiency: LC Filter Required with the Traditional Class-D Modulation Scheme
      14. 8.3.14 Ferrite Bead Filter Considerations
      15. 8.3.15 When to Use an Output Filter for EMI Suppression
      16. 8.3.16 AM Avoidance EMI Reduction
    4. 8.4 Device Functional Modes
      1. 8.4.1 Mono PBTL Mode
      2. 8.4.2 Mono BTL Mode (Single Channel Mode)
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Typical Application
        1. 9.1.1.1 Design Requirements
        2. 9.1.1.2 Detailed Design Procedure
          1. 9.1.1.2.1 Select the PWM Frequency
          2. 9.1.1.2.2 Select the Amplifier Gain and Master/Slave Mode
          3. 9.1.1.2.3 Select Input Capacitance
          4. 9.1.1.2.4 Select Decoupling Capacitors
          5. 9.1.1.2.5 Select Bootstrap Capacitors
        3. 9.1.1.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Mode
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Heat Sink Used on the EVM
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Related Documentation
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.4 PLIMIT Operation

The TPA3126D2 has a built-in voltage limiter that can be used to limit the output voltage level below the supply rail. The amplifier operates as if it was powered by a lower supply voltage, and thereby, limits the output power. Add a resistor divider from GVDD to ground to set the voltage at the PLIMIT pin. An external reference may also be used if tighter tolerance is required. Add a 1-µF capacitor from pin PLIMIT to ground to ensure stability.

TPA3126D2 POWER_LIMIT_example_los708.gifFigure 27. Power Limit Example

The PLIMIT circuit sets a limit on the output peak-to-peak voltage. This is done by limiting the duty cycle to a fixed maximum value. The limit can be considered as a "virtual" voltage rail which is lower than the supply connected to PVCC. The "virtual" rail is approximately four times the voltage at the PLIMIT pin. The output voltage can be used to calculate the maximum output power for a given maximum input voltage and speaker impedance.

Equation 2. TPA3126D2 EQ1_Pout_los708.gif

where

  • POUT (10%THD) = 1.25 × POUT (unclipped)
  • RL is the load resistance.
  • RS is the total series resistance including RDS(on), and output filter resistance.
  • VP is the peak amplitude, which is limited by the "virtual" voltage rail.

Table 3. Power Limit Example

PVCC (V) PLIMIT VOLTAGE (V)(1) R to GND R to GVDD OUTPUT VOLTAGE (Vrms)
24 V GVDD Open Short 17.9
24 V 3.3 45 kΩ 51 kΩ 12.67
24 V 2.25 24 kΩ 51 kΩ 9
12 V GVDD Open Short 10.33
12 V 2.25 24 kΩ 51 kΩ 9
12 V 1.5 18 kΩ 68 kΩ 6.3
(1) PLIMIT measurements taken with EVM gain set to 26 dB and input voltage set to 1 Vrms.