SLOS993A March 2018 – June 2018 TPA3138D2
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
PIN | I/O/P(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
NC | 1 | – | No Connect Pin. Can be shorted to PVCC or shorted to GND or left open. |
SD/FAULT | 2 | IO | TTL logic levels with compliance to AVCC. Shutdown logic input for audio amp (LOW , outputs Hi-Z; HIGH , outputs enabled). General fault reporting including Over-Temp, Over-Current, DC Detect. SD/FAULT= High, normal operation, SD/FAULT= Low, fault condition Device will auto-recover once the OT/OC/DC Fault has been removed. |
LINP | 3 | I | Positive audio input for left channel. Biased at 2.5 V. Connect to GND for PBTL mode. |
LINN | 4 | I | Negative audio input for left channel. Biased at 2.5 V. Connect to GND for PBTL mode. |
GAIN_SEL | 5 | I | Gain select least significant bit. TTL logic levels with compliance to AVDD. Low = 20 dB Gain, High = 26 dB Gain, Floating = 26 dB Gain. |
MODE_SEL | 6 | I | Mode select least significant bit. TTL logic levels with compliance to AVDD. Low = BD Mode/UV Threshold = 7.5 V, High = Low-Idle-Current 1SPW Mode/UV Threshold = 3.4V, Floating = Low-Idle-Current 1SPW Mode/UV threshold = 3.4V |
AVCC | 7 | P | Analog supply. |
GND | 8 | – | Analog signal ground. |
GVDD | 9 | O | FET gate drive supply. Nominal voltage is 5 V. |
PLIMIT | 10 | I | Power limiter level control. Connect a resistor divider from GVDD to GND to set power limit. Connect directly to GVDD for no power limit. |
RINN | 11 | I | Negative audio input for right channel. Biased at 2.5 V. |
RINP | 12 | I | Positive audio input for right channel. Biased at 2.5 V. |
NC | 13 | – | No Connect Pin. Can be shorted to PVCC or shorted to GND or left open. |
AGND | 14 | – | Analog signal ground. Connect to the thermal pad. |
PVCCR | 15, 16 | P | Power supply for right channel H-bridge. Right channel and left channel power supply inputs are connected internally. |
BSPR | 17 | P | Bootstrap supply (BST) for right channel, positive high-side FET. |
OUTPR | 18 | O | Class-D H-bridge positive output for right channel. |
GND | 19 | – | Power ground for the H-bridges. |
OUTNR | 20 | O | Class-D H-bridge negative output for right channel. |
BSNR | 21 | P | Bootstrap supply (BST) for right channel, negative high-side FET. |
BSNL | 22 | P | Bootstrap supply (BST) for left channel, negative high-side FET. |
OUTNL | 23 | O | Class-D H-bridge negative output for left channel. |
GND | 24 | – | Power ground for the H-bridges. |
OUTPL | 25 | O | Class-D H-bridge positive output for left channel. |
BSPL | 26 | P | Bootstrap supply (BST) for left channel, positive high-side FET. |
PVCCL | 27, 28 | P | Power supply for left channel H-bridge. Right channel and left channel power supply inputs are connected internally. |
Thermal Pad | – | Connect to GND for best thermal and electrical performance |