SLOS810A October   2019  – August 2020 TPA3139D2

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics,
      1. 6.7.1 Bridge -Tied Load (BTL)
      2. 6.7.2 Paralleled Bridge -Tied Load (PBTL)
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Gain
      2. 7.3.2  SD/ FAULT and MUTE Operation
      3. 7.3.3  PLIMIT
      4. 7.3.4  Spread Spectrum and De-Phase Control
      5. 7.3.5  GVDD Supply
      6. 7.3.6  DC Detect
      7. 7.3.7  PBTL Select
      8. 7.3.8  Short-Circuit Protection and Automatic Recovery Feature
      9. 7.3.9  Over-Temperature Protection (OTP)
      10. 7.3.10 Over-Voltage Protection (OVP)
      11. 7.3.11 Under-Voltage Protection (UVP)
    4. 7.4 Device Functional Modes
      1. 7.4.1 MODE_SEL = LOW: BD Modulation
      2. 7.4.2 MODE_SEL = HIGH: Low-Idle-Current 1SPW Modulation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 PCB Material Recommendation
        2. 8.2.1.2 PVCC Capacitor Recommendation
        3. 8.2.1.3 Decoupling Capacitor Recommendations
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Ferrite Bead Filter Considerations
        2. 8.2.2.2 Efficiency: LC Filter Required with the Traditional Class-D Modulation Scheme
        3. 8.2.2.3 When to Use an Output Filter for EMI Suppression
        4. 8.2.2.4 Input Resistance
        5. 8.2.2.5 Input Capacitor, Ci
        6. 8.2.2.6 BSN and BSP Capacitors
        7. 8.2.2.7 Differential Inputs
        8. 8.2.2.8 Using Low-ESR Capacitors
      3. 8.2.3 Application Performance Curves
        1. 8.2.3.1 EN55013 Radiated Emissions Results
        2. 8.2.3.2 EN55022 Conducted Emissions Results
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply Decoupling, CS
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.1 Overview

The TPA3139D2 is designed as a low-idle-power, cost-effective, general-purpose Class-D audio amplifier. The fast turn-on time (15-ms) along with MUTE function allows TPA3139D2 to quickly power up while avoiding pop. The built-in spread spectrum control scheme efficiently suppresses EMI and enables the use of ferrite beads instead of inductors for ≤ 2 x 10 W applications.

To facilitate system design, the TPA3139D2 needs only one power supply between 3.5 V and 14.4 V for operation. An internal voltage regulator provides suitable voltage levels for the gate driver, digital, and low-voltage analog circuitry. For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin (BSxx) to the power-stage output pin (OUTxx). When the power-stage output is low, the bootstrap capacitor is charged through an internal diode connected between the gate-drive power-supply pin (GVDD) and the bootstrap pins. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM switching frequencies in the datasheet specified range, use ceramic capacitors with at least 220-nF capacitance, size 0603 or 0805, for the bootstrap supply. These capacitors ensure sufficient energy storage, even during clipped low frequency audio signals, to keep the high-side power stage FET (LDMOS) fully turned on during the remaining part of its ON cycle.

The audio signal path, including the gate drive and output stage, is designed as identical, independent full-bridges. All decoupling capacitors should be placed as close as possible to their associated pins. The physical loop with the power supply pins, decoupling capacitors, and GND return path to the device pins must be kept as short as possible, and with as little area as possible to minimize induction.

Special attention should be paid to the power-stage power supply; this includes component selection, PCB placement, and routing. For optimal electrical performance, EMI compliance, and system reliability, each PVCC pin should be decoupled with ceramic capacitors that are placed as close as possible to each supply pin. It is recommended to follow the PCB layout of the TPA3139D2 reference design. For additional information on recommended power supply and required components, see the application diagrams in this data sheet.

The PVCC power supply should have low output impedance and low noise. The power-supply ramp and SD/ FAULT release sequence is not critical for device reliability as facilitated by the internal power-on-reset circuit, but it is recommended to release SD/ FAULT after the power supply is settled for minimum turn-on audible artifacts.