SLASEF0 November   2022 TPA3223

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
    1. 6.1 Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Audio Characteristics (BTL)
    7. 7.7 Audio Characteristics (PBTL)
    8. 7.8 Typical Characteristics, BTL Configuration, AD-mode
    9. 7.9 Typical Characteristics, PBTL Configuration, AD-mode
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Feature Description
      1. 9.3.1 Input Configuration, Gain Setting And Primary / Peripheral Operation
      2. 9.3.2 Gain Setting And Clock Synchronization
      3. 9.3.3 PWM Modulation
      4. 9.3.4 Oscillator
      5. 9.3.5 Input Impedance
      6. 9.3.6 Error Reporting
    4. 9.4 Device Functional Modes
      1. 9.4.1 Powering Up
        1. 9.4.1.1 Startup Ramp Time
      2. 9.4.2 Powering Down
        1. 9.4.2.1 Power Down Ramp Time
      3. 9.4.3 Device Reset
      4. 9.4.4 Device Soft Mute
      5. 9.4.5 Device Protection System
        1. 9.4.5.1 Overload and Short Circuit Current Protection
        2. 9.4.5.2 Signal Clipping and Pulse Injector
        3. 9.4.5.3 DC Speaker Protection
        4. 9.4.5.4 Pin-to-Pin Short Circuit Protection (PPSC)
        5. 9.4.5.5 Overtemperature Protection OTW and OTE
        6. 9.4.5.6 Undervoltage Protection (UVP), Overvoltage Protection (OVP), and Power-on Reset (POR)
        7. 9.4.5.7 Fault Handling
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Stereo BTL Application
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedures
          1. 10.2.1.2.1 Decoupling Capacitor Recommendations
          2. 10.2.1.2.2 PVDD Capacitor Recommendation
          3. 10.2.1.2.3 BST capacitors
          4. 10.2.1.2.4 PCB Material Recommendation
      2. 10.2.2 Application Curves
      3. 10.2.3 Typical Application, Differential (2N), AD-Mode PBTL (Outputs Paralleled after LC filter)
        1. 10.2.3.1 Design Requirements
    3. 10.3 Power Supply Recommendations
      1. 10.3.1 Power Supplies
        1. 10.3.1.1 VDD Supply
        2. 10.3.1.2 AVDD and GVDD Supplies
        3. 10.3.1.3 PVDD Supply
        4. 10.3.1.4 BST Supply
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Examples
        1. 10.4.2.1 BTL Application Printed Circuit Board Layout Example
        2. 10.4.2.2 PBTL (Outputs Paralleled after LC filter) Application Printed Circuit Board Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.3.2 Gain Setting And Clock Synchronization

The gain of TPA3223 is set by the voltage divider connected to the GAIN/CLKSYNC control pin. Clock synchronization configuration is also controlled by the same pin. An internal ADC is used to detect the 8 input states. The first four stages sets the GAIN in Primary mode in gains of 20, 23.5, 32 and 36 dB respectively, while the next four stages sets the GAIN in peripheral mode in gains of 20, 23.5, 32 and 36 dB respectively. The gain setting is latched when RESET goes high and cannot be changed while RESET is high. Table 9-1 shows the recommended resistor values, the state and gain:

Table 9-1 Clock Synchronization Configuration
Primary / Peripheral Mode Gain R1 (to GND) R2 (to AVDD) Differential Input Signal Level
(each input pin)		 Single Ended Input Signal Level
Primary 20 dB 5.6 kΩ OPEN 2 VRMS 2 VRMS
Primary 23.5 dB 20 kΩ 100 kΩ 1 VRMS 2 VRMS
Primary 32 dB 39 kΩ 100 kΩ 0.5 VRMS 1 VRMS
Primary 36 dB 47 kΩ 75 kΩ 0.32 VRMS 0.63 VRMS
Peripheral 20 dB 51 kΩ 51 kΩ 2 VRMS 2 VRMS
Peripheral 23.5 dB 75 kΩ 47 kΩ 1 VRMS 2 VRMS
Peripheral 32 dB 100 kΩ 39 kΩ 0.5 VRMS 1 VRMS
Peripheral 36 dB 100 kΩ 16 kΩ 0.32 VRMS 0.63 VRMS
Figure 9-5 Clock Synchronization Setup

For easy multi-channel system design TPA3223 has a Clock Synchronization feature that allows automatic synchronization of multiple peripheral devices operated at the PWM switching frequency of a Primary device. Using clock synchronization benefits system noise performance by eliminating spurious crosstalk sum and difference tones due to unsynchronized channel-to-channel switching frequencies. Furthermore, the Clock Synchronization scheme is designed to interleave switching of the individual channels in a multi-channel system such that the power supply current ripple frequency is moved to a higher frequency, which reduces the RMS ripple current in the power supply bulk capacitors.

The Clock Synchronization scheme and the interleaving of the output stage switching are automatically configured by connecting the OSCx pins between a Primary and multiple peripheral devices. There are two different configurations of peripheral devices (secondary or tertiary) depending on how the OSCx pins are connected. Connect the OSCM of the Primary device to the OSCM of a peripheral device and the OSCP of the Primary device to the OSCP pin of a peripheral device to configure as a secondary. Connect the OSCM of the Primary device to the OSCP of a peripheral device and the OSCP of the Primary device to the OSCM pin of a peripheral device to configure as a tertiary. The Primary, secondary and tertiary PWM switching is 30 degrees out of phase with each other. All switching channels are automatically synchronized by releasing RESET on all devices at the same time.

Figure 9-6 Gain and Primary PCB Implementation

Placement on the PCB and connection of multiple TPA3223 devices in a multi channel system is illustrated in Figure 9-6. Peripheral devices must be placed on either side of the Primary device, with a secondary device on one side of the Primary device, and a tertiary device on the other. In systems with more than 3 TPA3223 devices, the Primary must be in the middle, and every second peripheral device must be a secondary or tertiary as illustrated in Figure 9-6. A 47 kΩ pull up resistor to AVDD must be connected to the Primary device OSCM output and a 47 kΩ pull down resistor to GND must be connected to the Primary OSCP CLK outputs.