SLASEF0 November   2022 TPA3223

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
    1. 6.1 Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Audio Characteristics (BTL)
    7. 7.7 Audio Characteristics (PBTL)
    8. 7.8 Typical Characteristics, BTL Configuration, AD-mode
    9. 7.9 Typical Characteristics, PBTL Configuration, AD-mode
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Feature Description
      1. 9.3.1 Input Configuration, Gain Setting And Primary / Peripheral Operation
      2. 9.3.2 Gain Setting And Clock Synchronization
      3. 9.3.3 PWM Modulation
      4. 9.3.4 Oscillator
      5. 9.3.5 Input Impedance
      6. 9.3.6 Error Reporting
    4. 9.4 Device Functional Modes
      1. 9.4.1 Powering Up
        1. 9.4.1.1 Startup Ramp Time
      2. 9.4.2 Powering Down
        1. 9.4.2.1 Power Down Ramp Time
      3. 9.4.3 Device Reset
      4. 9.4.4 Device Soft Mute
      5. 9.4.5 Device Protection System
        1. 9.4.5.1 Overload and Short Circuit Current Protection
        2. 9.4.5.2 Signal Clipping and Pulse Injector
        3. 9.4.5.3 DC Speaker Protection
        4. 9.4.5.4 Pin-to-Pin Short Circuit Protection (PPSC)
        5. 9.4.5.5 Overtemperature Protection OTW and OTE
        6. 9.4.5.6 Undervoltage Protection (UVP), Overvoltage Protection (OVP), and Power-on Reset (POR)
        7. 9.4.5.7 Fault Handling
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Stereo BTL Application
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedures
          1. 10.2.1.2.1 Decoupling Capacitor Recommendations
          2. 10.2.1.2.2 PVDD Capacitor Recommendation
          3. 10.2.1.2.3 BST capacitors
          4. 10.2.1.2.4 PCB Material Recommendation
      2. 10.2.2 Application Curves
      3. 10.2.3 Typical Application, Differential (2N), AD-Mode PBTL (Outputs Paralleled after LC filter)
        1. 10.2.3.1 Design Requirements
    3. 10.3 Power Supply Recommendations
      1. 10.3.1 Power Supplies
        1. 10.3.1.1 VDD Supply
        2. 10.3.1.2 AVDD and GVDD Supplies
        3. 10.3.1.3 PVDD Supply
        4. 10.3.1.4 BST Supply
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Examples
        1. 10.4.2.1 BTL Application Printed Circuit Board Layout Example
        2. 10.4.2.2 PBTL (Outputs Paralleled after LC filter) Application Printed Circuit Board Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

PVDD = 42 V, VDD = 5 V, GVDD = 5 V, AVDD = 5 V, TC (Case temperature) = 75 °C, fS = 480 kHz, unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE AND CURRENT CONSUMPTION
IVDD VDD supply current Operating, no audio signal, VDD = 5 V 150 µA
IVDD Reset mode, VDD = 5 V 5 µA
IGVDD Gate-supply current. AD-mode modulation 50% duty cycle, VDD = 5 V 23 mA
IGVDD Reset mode, VDD = 5 V 5 µA
IPVDD Total PVDD idle current, AD-mode modulation, BTL 50% duty cycle with recommended output filter 45 mA
IPVDD Total PVDD idle current, AD-mode modulation, BTL 50% duty cycle with recommended output filter, TC = 25 ºC 35 mA
IPVDD Total PVDD idle current, AD-mode modulation, BTL Reset mode, No switching 1 mA
ANALOG INPUTS
G Inverting voltage Gain, VOUT/VIN(Primary Clock synchronized device configuration) R1 = 5.6 kΩ, R2 = OPEN 20 dB
R1 = 20 kΩ, R2 = 100 kΩ 23.5
R1 = 39 kΩ, R2 = 100 kΩ 32
R1 = 47 kΩ, R2 = 75 kΩ 36
Inverting voltage Gain, VOUT/VIN(Peripheral clock synchronized device configuration R1 = 51 kΩ, R2 = 51 kΩ 20
R1 = 75 kΩ, R2 = 47 kΩ 23.5
R1 = 100 kΩ, R2 = 39 kΩ 32
R1 = 100 kΩ, R2 = 16 kΩ 36
RIN Input resistance G = 20 dB 48 kΩ
G = 23.5 dB 24
G = 32 dB 12
G = 36 dB 7.3
OSCILLATOR
fOSC(IO)(1) Nominal, Primary Mode FPWM × 6 2.76 2.88 3 MHz
AM1, Primary Mode 3.06 3.198 3.33
AM2, Primary Mode 3.45 3.6 3.75
VIH High level input voltage 2.7 V
VIL Low level input voltage 0.7 V
EXTERNAL OSCILLATOR (Peripheral Mode)

OUTPUT-STAGE MOSFETs
RDS(on) Drain-to-source resistance, low side (LS) TJ = 25 °C, Excludes metallization resistance,
GVDD = 5 V		 60 mΩ
Drain-to-source resistance, high side (HS) 60 mΩ
I/O PROTECTION
Vuvp,AVDD Undervoltage protection limit, AVDD 4 V
Vuvp,AVDD,hyst Undervoltage protection hysteresis, AVDD 0.2 V
Vuvp,PVDD Undervoltage protection limit, PVDD_x 9.1 V
Vuvp,PVDD,hyst Undervoltage protection hysteresis, PVDD_x 0.6 V
Vovp,PVDD Overvoltage protection limit, PVDD_x 46 V
Vovp,PVDD,hyst Overvoltage protection hysteresis, PVDD_x 0.85 V
OTW Overtemperature warning, OTW_CLIP 125 °C
OTWhyst Temperature drop needed below OTW temperature for OTW_CLIP to be inactive after OTW event. 20 °C
OTE Overtemperature error 155 °C
OTEhyst A reset needs to occur for FAULT to be released following an OTE event 20 °C
OTE-OTW(differential) OTE-OTW differential 25 °C
OLPC Overload protection counter fPWM = 480 kHz (1024 PWM cycles) 2.2 ms
IOC, BTL Overcurrent limit protection, speaker load current Nominal peak current in 1 Ω load 10 A
IOC, PBTL Overcurrent limit protection, speaker output current Nominal peak current in 1 Ω load 20 A
IOCT Overcurrent response time Time from switching transition to flip-state induced by overcurrent. 150 ns
STATIC DIGITAL SPECIFICATIONS
VIH High level input voltage RESET 2.3 V
VIL Low level input voltage 0.7 V
Ilkg Input leakage current OSCM, OSCP, RESET 100 μA
OTW/SHUTDOWN (FAULT)
RINT_PU Internal pullup resistance, OTW_CLIP to AVDD, FAULT to AVDD 26 kΩ
VOH High level output voltage Internal pullup resistor 4.5 5 5.5 V
VOL Low level output voltage IO = 4 mA 200 500 mV
(1) Nominal, AM1 and AM2 use same internal oscillator with fixed ratio 4 : 4.5 : 5