SLASEM8A January   2019  – March 2019 TPA3255-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Total Harmonic Distortion
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Audio Characteristics (BTL)
    7. 6.7  Audio Characteristics (SE)
    8. 6.8  Audio Characteristics (PBTL)
    9. 6.9  Typical Characteristics, BTL Configuration
    10. 6.10 Typical Characteristics, SE Configuration
    11. 6.11 Typical Characteristics, PBTL Configuration
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Error Reporting
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Protection System
        1. 8.4.1.1 Overload and Short Circuit Current Protection
        2. 8.4.1.2 Signal Clipping and Pulse Injector
        3. 8.4.1.3 DC Speaker Protection
        4. 8.4.1.4 Pin-to-Pin Short Circuit Protection (PPSC)
        5. 8.4.1.5 Overtemperature Protection OTW and OTE
        6. 8.4.1.6 Undervoltage Protection (UVP) and Power-on Reset (POR)
        7. 8.4.1.7 Fault Handling
        8. 8.4.1.8 Device Reset
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Stereo BTL Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedures
          1. 9.2.1.2.1 Decoupling Capacitor Recommendations
          2. 9.2.1.2.2 PVDD Capacitor Recommendation
          3. 9.2.1.2.3 PCB Material Recommendation
          4. 9.2.1.2.4 Oscillator
      2. 9.2.2 Application Curves
      3. 9.2.3 Typical Application, Single Ended (1N) SE
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedures
        3. 9.2.3.3 Application Curves
      4. 9.2.4 Typical Application, Differential (2N) PBTL
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedures
        3. 9.2.4.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supplies
      1. 10.1.1 VDD Supply
      2. 10.1.2 GVDD_X Supply
      3. 10.1.3 PVDD Supply
    2. 10.2 Powering Up
    3. 10.3 Powering Down
    4. 10.4 Thermal Design
      1. 10.4.1 Thermal Performance
      2. 10.4.2 Thermal Performance with Continuous Output Power
      3. 10.4.3 Thermal Performance with Non-Continuous Output Power
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
      1. 11.2.1 BTL Application Printed Circuit Board Layout Example
      2. 11.2.2 SE Application Printed Circuit Board Layout Example
      3. 11.2.3 PBTL Application Printed Circuit Board Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4.1.7 Fault Handling

If a fault situation occurs while in operation, the device acts accordingly to the fault being a global or a channel fault. A global fault is a chip-wide fault situation and causes all PWM activity of the device to be shut down, and will assert FAULT low. A global fault is a latching fault and clearing FAULT and restarting operation requires resetting the device by toggling RESET. Deasserting RESET should never be allowed with excessive system temperature, so it is advised to monitor RESET by a system microcontroller and only allow releasing RESET (RESET high) if the CLIP_OTW signal is cleared (high). A channel fault results in shutdown of the PWM activity of the affected channel(s). Note that asserting RESET low forces the FAULT signal high, independent of faults being present.

Table 5. Error Reporting

Fault/Event Fault/Event Description Global or Channel Reporting Method Latched/Self Clearing Action needed to Clear Output FETs
PVDD_X UVP Voltage Fault Global FAULT pin Self Clearing Increase affected supply voltage HI-Z
VDD UVP
AVDD UVP
POR (DVDD UVP) Power On Reset Global FAULT pin Self Clearing Allow DVDD to rise HI-Z
BST_X UVP Voltage Fault Channel (Half Bridge) None Self Clearing Allow BST cap to recharge (lowside ON, VDD applied) HighSide off
OTW Thermal Warning Global OTW pin Self Clearing Cool below OTW threshold Normal operation
OTE Thermal Shutdown Global FAULT pin Latched Toggle RESET HI-Z
OLP (CB3C>1.7ms) OC Shutdown Channel FAULT pin Latched Toggle RESET HI-Z
Latched OC (47kΩ<ROC_ADJ<68kΩ) OC Shutdown Channel FAULT pin Latched Toggle RESET HI-Z
CB3C (22kΩ<ROC_ADJ<30kΩ) OC Limiting Channel None Self Clearing Reduce signal level or remove short Flip state, cycle by cycle at fs/3
Stuck at Fault(1) No OSC_IO activity in Slave Mode Global None Self Clearing Resume OSC_IO activity HI-Z
(1) Stuck at Fault occurs when input OSC_IO input signal frequency drops below minimum frequency given in the Electrical Characteristics table of this data sheet.