SLASEA8A February   2016  – October 2016 TPA3255

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Audio Characteristics (BTL)
    7. 7.7  Audio Characteristics (SE)
    8. 7.8  Audio Characteristics (PBTL)
    9. 7.9  Typical Characteristics, BTL Configuration
    10. 7.10 Typical Characteristics, SE Configuration
    11. 7.11 Typical Characteristics, PBTL Configuration
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Feature Description
      1. 9.3.1 Error Reporting
    4. 9.4 Device Functional Modes
      1. 9.4.1 Device Protection System
        1. 9.4.1.1 Overload and Short Circuit Current Protection
        2. 9.4.1.2 Signal Clipping and Pulse Injector
        3. 9.4.1.3 DC Speaker Protection
        4. 9.4.1.4 Pin-to-Pin Short Circuit Protection (PPSC)
        5. 9.4.1.5 Overtemperature Protection OTW and OTE
        6. 9.4.1.6 Undervoltage Protection (UVP) and Power-on Reset (POR)
        7. 9.4.1.7 Fault Handling
        8. 9.4.1.8 Device Reset
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Stereo BTL Application
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedures
          1. 10.2.1.2.1 Decoupling Capacitor Recommendations
          2. 10.2.1.2.2 PVDD Capacitor Recommendation
          3. 10.2.1.2.3 PCB Material Recommendation
          4. 10.2.1.2.4 Oscillator
      2. 10.2.2 Application Curves
      3. 10.2.3 Typical Application, Single Ended (1N) SE
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedures
        3. 10.2.3.3 Application Curves
      4. 10.2.4 Typical Application, Differential (2N) PBTL
        1. 10.2.4.1 Design Requirements
        2. 10.2.4.2 Detailed Design Procedures
        3. 10.2.4.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Power Supplies
      1. 11.1.1 VDD Supply
      2. 11.1.2 GVDD_X Supply
      3. 11.1.3 PVDD Supply
    2. 11.2 Powering Up
    3. 11.3 Powering Down
    4. 11.4 Thermal Design
      1. 11.4.1 Thermal Performance
      2. 11.4.2 Thermal Performance with Continuous Output Power
      3. 11.4.3 Thermal Performance with Non-Continuous Output Power
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Examples
      1. 12.2.1 BTL Application Printed Circuit Board Layout Example
      2. 12.2.2 SE Application Printed Circuit Board Layout Example
      3. 12.2.3 PBTL Application Printed Circuit Board Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Supply voltage BST_X to GVDD_X(2) –0.3 69 V
VDD to GND –0.3 13.2 V
GVDD_X to GND(2) –0.3 13.2 V
PVDD_X to GND(2) –0.3 69 V
DVDD to GND –0.3 4.2 V
AVDD to GND –0.3 8.5 V
VBG to GND -0.3 4.2 V
Interface pins OUT_X to GND(2) –0.3 69 V
BST_X to GND(2) –0.3 81.5 V
OC_ADJ, M1, M2, OSC_IOP, OSC_IOM, FREQ_ADJ, C_START, to GND –0.3 4.2 V
RESET, FAULT, CLIP_OTW to GND –0.3 4.2 V
INPUT_X to GND –0.3 7 V
Continuous sink current, RESET, FAULT, CLIP_OTW to GND 9 mA
TJ Operating junction temperature range 0 150 °C
Tstg Storage temperature range –40 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) These voltages represents the DC voltage + peak AC waveform measured at the terminal of the device in all conditions.

7.2 ESD Ratings

VALUE UNIT
VESD Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN TYP MAX UNIT
PVDD_x Half-bridge supply DC supply voltage, RL = 4Ω 18 51 53.5 V
DC supply voltage, RL ≥ 6Ω(1) 18 53.5 56.5
GVDD_x Supply for logic regulators and gate-drive circuitry DC supply voltage 10.8 12 13.2 V
VDD Digital regulator supply voltage DC supply voltage 10.8 12 13.2 V
RL(BTL) Load impedance Output filter inductance within recommended value range 3.4 4 Ω
RL(SE) 1.7 3
RL(PBTL) 1.7 2
LOUT(BTL) Output filter inductance Minimum output inductance at IOC 5 μH
LOUT(SE) 5
LOUT(PBTL) 5
FPWM PWM frame rate selectable for AM interference avoidance; 1% Resistor tolerance Nominal 430 450 470 kHz
AM1 475 500 525
AM2 575 600 625
R(FREQ_ADJ) PWM frame rate programming resistor Nominal; Master mode 29.7 30 30.3 kΩ
AM1; Master mode 19.8 20 20.2
AM2; Master mode 9.9 10 10.1
CPVDD PVDD close decoupling capacitors 1 μF
ROC Over-current programming resistor Resistor tolerance = 5%, RL = 4Ω 22 30 kΩ
Resistor tolerance = 5%, RL ≥ 6Ω, PVDD = 53.5V(1) 30
ROC(LATCHED) Over-current programming resistor Resistor tolerance = 5%, RL = 4Ω 47 64 kΩ
Resistor tolerance = 5%, RL ≥ 6Ω, PVDD = 53.5V(1) 64
V(FREQ_ADJ) Voltage on FREQ_ADJ pin for slave mode operation Slave mode 3.3 V
TJ Junction temperature 0 125 °C
(1) For load impedance ≥ 6Ω PVDD can be increased, provided a reduced over-current threshold is set

7.4 Thermal Information

THERMAL METRIC(1) TPA3255 UNIT
DDV 44-PINS HTSSOP
JEDEC STANDARD 4 LAYER PCB FIXED 85°C HEATSINK TEMPERATURE(2)
RθJA Junction-to-ambient thermal resistance 50.7 2.4(2) °C/W
RθJC(top) Junction-to-case (top) thermal resistance 0.36 0.3
RθJB Junction-to-board thermal resistance 24.4 n/a
ψJT Junction-to-top characterization parameter 0.19 0.5
ψJB Junction-to-board characterization parameter 24.2 n/a
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
(2) Thermal data are obtained with 85°C heat sink temperature using thermal compound with 0.7W/mK thermal conductivity and 2mil thickness. In this model heat sink temperature is considered to be the ambient temperature and only path for dissipation is to the heatsink.

7.5 Electrical Characteristics

PVDD_X = 51 V, GVDD_X = 12 V, VDD = 12 V, TC (Case temperature) = 75°C, fS = 450 kHz, unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION
DVDD Voltage regulator, only used as reference node VDD = 12 V 3 3.3 3.6 V
AVDD Voltage regulator, only used as reference node VDD = 12 V 7.75 V
IVDD VDD supply current Operating, 50% duty cycle 30 mA
Idle, reset mode 14
IGVDD_X Gate-supply current per full-bridge 50% duty cycle 44 mA
Reset mode 5
IPVDD_X PVDD idle current per full bridge 50% duty cycle with recommended output filter 24 mA
Reset mode, No switching 5 mA
VDD = 0V, GVDD_X = 0V 1.25 mA
ANALOG INPUTS
RIN Input resistance 20 kΩ
VIN Maximum input voltage swing, peak - peak 7 V
IIN Maximum input current 1 mA
G Inverting voltage Gain VOUT/VIN 21.5 dB
OSCILLATOR
fOSC(IO+) Nominal, Master Mode FPWM × 6 2.58 2.7 2.82 MHz
AM1, Master Mode 2.85 3 3.15
AM2, Master Mode 3.45 3.6 3.75
VIH High level input voltage 1.86 V
VIL Low level input voltage 1.45 V
OUTPUT-STAGE MOSFETs
RDS(on) Drain-to-source resistance, low side (LS) TJ = 25°C, Includes metallization resistance,
GVDD = 12 V		 85 100 mΩ
Drain-to-source resistance, high side (HS) 85 100 mΩ
I/O PROTECTION
Vuvp,VDD,GVDD Undervoltage protection limit, GVDD_x and VDD 8.7 V
Vuvp,VDD, GVDD,hyst (1) 0.6 V
Vuvp,PVDD Undervoltage protection limit, PVDD_x 14.5 V
Vuvp,PVDD,hyst (1) 1.4 V
OTW Overtemperature warning, CLIP_OTW(1) 110 120 130 °C
OTWhyst (1) Temperature drop needed below OTW temperature for CLIP_OTW to be inactive after OTW event. 20 °C
OTE(1) Overtemperature error 140 150 160 °C
OTEhyst (1) A reset needs to occur for FAULT to be released following an OTE event 15 °C
OTE-OTW(differential) (1) OTE-OTW differential 30 °C
OLPC Overload protection counter fPWM = 450 kHz (1024 PWM cycles) 2.3 ms
IOC Overcurrent limit protection Resistor – programmable, nominal peak current in 1Ω load, ROCP = 22 kΩ 17 A
Resistor – programmable, nominal peak current in 1Ω load, ROCP = 30 kΩ 13
IOC(LATCHED) Overcurrent limit protection Resistor – programmable, peak current in 1Ω load, ROCP = 47kΩ 17 A
Resistor – programmable, peak current in 1Ω load, ROCP = 64kΩ 13
IDCspkr DC Speaker Protection Current Threshold BTL current imbalance threshold 1.5 A
IOCT Overcurrent response time Time from switching transition to flip-state induced by overcurrent. 150 ns
IPD Output pulldown current of each half Connected when RESET is active to provide bootstrap charge. Not used in SE mode. 3 mA
STATIC DIGITAL SPECIFICATIONS
VIH High level input voltage M1, M2, OSC_IOP, OSC_IOM, RESET 1.9 V
VIL Low level input voltage 0.8 V
Ilkg Input leakage current 100 μA
OTW/SHUTDOWN (FAULT)
RINT_PU Internal pullup resistance, CLIP_OTW to DVDD, FAULT to DVDD 20 26 32 kΩ
VOH High level output voltage Internal pullup resistor 3 3.3 3.6 V
VOL Low level output voltage IO = 4 mA 10 500 mV
Device fanout CLIP_OTW, FAULT No external pullup 30 devices
(1) Specified by design.

7.6 Audio Characteristics (BTL)

PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 51 V, GVDD_X = 12 V, RL = 4 Ω, fS = 450 kHz, ROC = 22 kΩ, TC = 75°C, Output Filter: LDEM = 10 μH, CDEM = 1 µF, mode = 00, AES17 + AUX-0025 measurement filters,unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PO Power output per channel RL = 4 Ω, 10% THD+N 315 W
RL = 6 Ω, 10% THD+N, PVDD = 53.5V 250
RL = 8 Ω, 10% THD+N, PVDD = 53.5V 195
RL = 4 Ω, 1% THD+N 255
RL = 6 Ω, 1% THD+N, PVDD = 53.5V 200
RL = 8 Ω, 1% THD+N, PVDD = 53.5V 155
THD+N Total harmonic distortion + noise 1 W 0.006%
Vn Output integrated noise A-weighted, AES17 filter, Input Capacitor Grounded 85 μV
|VOS| Output offset voltage Inputs AC coupled to GND 15 60 mV
SNR Signal-to-noise ratio(1) 112 dB
DNR Dynamic range 113 dB
Pidle Power dissipation due to Idle losses (IPVDD) PO = 0, 4 channels switching(2) 2.5 W
(1) SNR is calculated relative to 1% THD+N output level.
(2) Actual system idle losses also are affected by core losses of output inductors.

7.7 Audio Characteristics (SE)

PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 51 V, GVDD_X = 12 V, RL = 2 Ω, fS = 450 kHz, ROC = 22 kΩ, TC = 75°C, Output Filter: LDEM = 15 μH, CDEM = 1 µF, MODE = 11, AES17 + AUX-0025 measurement filters, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PO Power output per channel RL = 2 Ω, 10% THD+N 148 W
RL = 3 Ω, 10% THD+N, PVDD = 53.5V 120
RL = 4 Ω, 10% THD+N, PVDD = 53.5V 95
RL = 2 Ω, 1% THD+N 120
RL = 3 Ω, 1% THD+N, PVDD = 53.5V 98
RL = 4 Ω, 1% THD+N, PVDD = 53.5V 77
THD+N Total harmonic distortion + noise 1 W 0.04%
Vn Output integrated noise A-weighted, AES17 filter, Input Capacitor Grounded 160 μV
SNR Signal to noise ratio(1) A-weighted 101 dB
DNR Dynamic range A-weighted 101 dB
Pidle Power dissipation due to idle losses (IPVDD) PO = 0, 4 channels switching(2) 2 W
(1) SNR is calculated relative to 1% THD+N output level.
(2) Actual system idle losses are affected by core losses of output inductors.

7.8 Audio Characteristics (PBTL)

PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 51 V, GVDD_X = 12 V, RL = 2 Ω, fS = 450 kHz, ROC = 22 kΩ, TC = 75°C, Output Filter: LDEM = 10 μH, CDEM = 1 µF, MODE = 10, AES17 + AUX-0025 measurement filters, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PO Power output per channel RL = 2 Ω, 10% THD+N 605 W
RL = 3 Ω, 10% THD+N, PVDD = 53.5V 500
RL = 4 Ω, 10% THD+N, PVDD = 53.5V 390
RL = 2 Ω, 1% THD+N 495
RL = 3 Ω, 1% THD+N, PVDD = 53.5V 405
RL = 4 Ω, 1% THD+N, PVDD = 53.5V 315
THD+N Total harmonic distortion + noise 1 W 0.008%
Vn Output integrated noise A-weighted, AES17 filter, Input Capacitor Grounded 70 μV
SNR Signal to noise ratio(1) A-weighted 114 dB
DNR Dynamic range A-weighted 114 dB
Pidle Power dissipation due to idle losses (IPVDD) PO = 0, 4 channels switching(2) 2.5 W
(1) SNR is calculated relative to 1% THD+N output level.
(2) Actual system idle losses are affected by core losses of output inductors.

7.9 Typical Characteristics, BTL Configuration

All Measurements taken at audio frequency = 1 kHz, PVDD_X = 51 V, GVDD_X = 12 V, RL = 4 Ω, fS = 450 kHz, ROC = 22 kΩ, TC = 75°C, Output Filter: LDEM = 10 μH, CDEM = 1 µF, mode = 00, AES17 + AUX-0025 measurement filters,unless otherwise noted.
TPA3255 D001_SLASEA8.gif
RL = 4 Ω P = 1W, 25W, 150W TC = 75°C
PVDD = 51V
Figure 1. Total Harmonic Distortion+Noise vs Frequency
TPA3255 D003_SLASEA8.gif
A.
RL = 8 Ω P = 1W, 25W, 100W TC = 75°C
PVDD = 53.5V
Figure 3. Total Harmonic Distortion+Noise vs Frequency
TPA3255 D005_SLASEA8.gif
RL = 4 Ω, 6 Ω, 8 Ω TC = 75°C PVDD = 51V
Figure 5. Total Harmonic Distortion + Noise vs Output Power
TPA3255 D007_SLASEA8.gif
RL = 4 Ω, 6 Ω, 8 Ω THD+N = 10% TC = 75°C
Figure 7. Output Power vs Supply Voltage
TPA3255 D009_SLASEA8.gif
RL = 4 Ω, 6 Ω, 8 Ω THD+N = 10% TC = 75°C
Figure 9. System Efficiency vs Output Power
TPA3255 D011_SLASEA8.gif
RL = 4 Ω, 6 Ω, 8 Ω THD+N = 10% TC = 75°C
Figure 11. Output Power vs Case Temperature
TPA3255 D002_SLASEA8.gif
RL = 4 Ω P = 1W, 25W, 150W TC = 75°C
AUX-0025 filter, 80 kHz analyzer BW PVDD = 51V
Figure 2. Total Harmonic Distortion+Noise vs Frequency
TPA3255 D004_SLASEA8.gif
A.
RL = 8 Ω P = 1W, 25W, 100W TC = 75°C
AUX-0025 filter, 80 kHz analyzer BW PVDD = 53.5V
Figure 4. Total Harmonic Distortion+Noise vs Frequency
TPA3255 D006_SLASEA8.gif
A.
RL = 6 Ω, 8 Ω TC = 75°C PVDD = 53.5V
Figure 6. Total Harmonic Distortion + Noise vs Output Power
TPA3255 D008_SLASEA8.gif
RL = 4 Ω, 6 Ω, 8 Ω THD+N = 1% TC = 75°C
Figure 8. Output Power vs Supply Voltage
TPA3255 D010_SLASEA8.gif
RL = 4 Ω, 6 Ω, 8 Ω THD+N = 10% TC = 75°C
Figure 10. System Power Loss vs Output Power
TPA3255 D012_SLASEA8.gif
4 Ω, VREF = 36.06 V (1% Output power) FFT = 16384
AUX-0025 filter, 80 kHz analyzer BW TC = 75°C
Figure 12. Noise Amplitude vs Frequency

7.10 Typical Characteristics, SE Configuration

All Measurements taken at audio frequency = 1 kHz, PVDD_X = 51 V, GVDD_X = 12 V, RL = 3 Ω, fS = 450 kHz, ROC = 22 kΩ, TC = 75°C, Output Filter: LDEM = 15 μH, CDEM = 680 nF, MODE = 11, AES17 + AUX-0025 measurement filters, unless otherwise noted.
TPA3255 D013_SLASEA8.gif
RL = 2Ω, 3Ω, 4Ω TC = 75°C
Figure 13. Total Harmonic Distortion+Noise vs Output Power
TPA3255 D015_SLASEA8.gif
RL = 3Ω P = 1W, 20W, 50W TC = 75°C
AUX-0025 filter, 80 kHz analyzer BW
Figure 15. Total Harmonic Distortion+Noise vs Frequency
TPA3255 D017_SLASEA8.gif
RL = 2Ω, 3Ω, 4Ω THD+N = 1% TC = 75°C
Figure 17. Output Power vs Supply Voltage
TPA3255 D014_SLASEA8.gif
RL = 3Ω P = 1W, 20W, 50W TC = 75°C
Figure 14. Total Harmonic Distortion+Noise vs Frequency
TPA3255 D016_SLASEA8.gif
RL = 2Ω, 3Ω, 4Ω THD+N = 10% TC = 75°C
Figure 16. Output Power vs Supply Voltage
TPA3255 D018_SLASEA8.gif
RL = 2Ω, 3Ω, 4Ω THD+N = 10% TC = 75°C
Figure 18. Output Power vs Case Temperature

7.11 Typical Characteristics, PBTL Configuration

All Measurements taken at audio frequency = 1 kHz, PVDD_X = 51V, GVDD_X = 12 V, RL = 2Ω, fS = 450 kHz, ROC = 22 kΩ, TC = 75°C, Output Filter: LDEM = 10μH, CDEM = 1 µF, MODE = 10, AES17 + AUX-0025 measurement filters, unless otherwise noted.
TPA3255 D019_SLASEA8.gif
RL = 2Ω, 3Ω, 4Ω TC = 75°C
Figure 19. Total Harmonic Distortion+Noise vs Output Power
TPA3255 D021_SLASEA8.gif
RL = 2Ω P = 1W, 50W, 375W TC = 75°C
AUX-0025 filter, 80 kHz analyzer BW
Figure 21. Total Harmonic Distortion+Noise vs Frequency
TPA3255 D023_SLASEA8.gif
RL = 2Ω, 3Ω, 4Ω THD+N = 1% TC = 75°C
Figure 23. Output Power vs Supply Voltage
TPA3255 D020_SLASEA8.gif
RL = 2Ω P = 1W, 50W, 375W TC = 75°C
Figure 20. Total Harmonic Distortion+Noise vs Frequency
TPA3255 D022_SLASEA8.gif
RL = 2Ω, 3Ω, 4Ω THD+N = 10% TC = 75°C
Figure 22. Output Power vs Supply Voltage
TPA3255 D024_SLASEA8.gif
RL = 2Ω, 3Ω, 4Ω THD+N = 10% TC = 75°C
Figure 24. Output Power vs Case Temperature