SLOS490C July   2006  – November 2015

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Operating Characteristics
    7. 7.7 Dissipation Ratings
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Fully Differential Amplifiers
        1. 9.3.1.1 Advantages of Fully Differential Amplifiers
      2. 9.3.2 Fully Differential Amplifier Efficiency and Thermal Information
      3. 9.3.3 Differential Output Versus Single-Ended Output
    4. 9.4 Device Functional Modes
      1. 9.4.1 Summing Input Signals With The TPA6205A1
        1. 9.4.1.1 Summing Two Differential Input Signals
        2. 9.4.1.2 Summing a Differential Input Signal and a Single-Ended Input Signal
        3. 9.4.1.3 Summing Two Single-Ended Input Signals
      2. 9.4.2 Shutdown Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 TPA6205A1 With Differential Input
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Selecting Components
            1. 10.2.1.2.1.1 Resistors (RF and RI)
            2. 10.2.1.2.1.2 Bypass Capacitor (CBYPASS) and Start-Up Time
            3. 10.2.1.2.1.3 Input Capacitor (CI)
            4. 10.2.1.2.1.4 Decoupling Capacitor (CS)
          2. 10.2.1.2.2 Using Low-ESR Capacitors
        3. 10.2.1.3 Application Curves
      2. 10.2.2 TPA6205A1 With Differential Input and Input Capacitors
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curves
      3. 10.2.3 TPA6205A1 With Single-Ended Input
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
        3. 10.2.3.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Power Supply Decoupling Capacitors
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Community Resources
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Detailed Description

9.1 Overview

The TPA6205A1 is a 1.25-W mono fully differential amplifier. The devices operates in the range of 2.5 V to 5.5 V and with at least 8-Ω impedance load. It's fully differential input allows it to avoid using input coupling capacitors and improves its RF-immunity.

9.2 Functional Block Diagram

SLOS490TPA6205A1 front_page_app_circ_01_slos490.gif

9.3 Feature Description

9.3.1 Fully Differential Amplifiers

The TPA6205A1 is a fully differential amplifier with differential inputs and outputs. The fully differential amplifier consists of a differential amplifier and a common-mode amplifier. The differential amplifier ensures that the amplifier outputs a differential voltage that is equal to the differential input times the gain. The common-mode feedback ensures that the common-mode voltage at the output is biased around VDD/2 regardless of the common-mode voltage at the input.

9.3.1.1 Advantages of Fully Differential Amplifiers

  • Input coupling capacitors not required: A fully differential amplifier with good CMRR, like the TPA6205A1, allows the inputs to be biased at voltage other than mid-supply. For example, if a DAC has mid-supply lower than the mid-supply of the TPA6205A1, the common-mode feedback circuit adjusts for that, and the TPA6205A1 outputs are still biased at mid-supply of the TPA6205A1. The inputs of the TPA6205A1 can be biased from 0.5 V to VDD – 0.8 V. If the inputs are biased outside of that range, input coupling capacitors are required.
  • Mid-supply bypass capacitor, C(BYPASS), not required: The fully differential amplifier does not require a bypass capacitor. This is because any shift in the mid-supply affects both positive and negative channels equally and cancels at the differential output. However, removing the bypass capacitor slightly worsens power supply rejection ratio (kSVR), but a slight decrease of kSVR may be acceptable when an additional component can be eliminated (see Figure 17).
  • Better RF-immunity: GSM handsets save power by turning on and shutting off the RF transmitter at a rate of 217 Hz. The transmitted signal is picked-up on input and output traces. The fully differential amplifier cancels the signal much better than the typical audio amplifier.

9.3.2 Fully Differential Amplifier Efficiency and Thermal Information

Class-AB amplifiers are inefficient. The primary cause of these inefficiencies is voltage drop across the output stage transistors. There are two components of the internal voltage drop. One is the headroom or DC voltage drop that varies inversely to output power. The second component is due to the sinewave nature of the output. The total voltage drop can be calculated by subtracting the RMS value of the output voltage from VDD. The internal voltage drop multiplied by the average value of the supply current, IDD(avg), determines the internal power dissipation of the amplifier.

An easy-to-use equation to calculate efficiency starts Although the voltages and currents for SE and BTL out as being equal to the ratio of power from the are sinusoidal in the load, currents from the supply power supply to the power delivered to the load. To are very different between SE and BTL accurately calculate the RMS and average values of configurations. In an SE application the current power in the load and in the amplifier, the current and waveform is a half-wave rectified shape, whereas in voltage waveform shapes must first be understood BTL it is a full-wave rectified waveform. This means (see Figure 27). RMS conversion factors are different. Keep in mind that for most of the waveform both the push and pull transistors are not on at the same time, which supports the fact that each amplifier in the BTL device only draws current from the supply for half the waveform. Equation 1 through Equation 7 are the basis for calculating amplifier efficiency.

SLOS490TPA6205A1 sc_04_vltg_and_crrnt_wvfrms_btl_amps_slos490.gif Figure 27. Voltage and Current Waveforms for BTL Amplifiers
Equation 1. SLOS490TPA6205A1 eq_08_slos490.gif

where

  • SLOS490TPA6205A1 eq_09_slos490.gif
  • SLOS490TPA6205A1 eq_10_slos490.gif
  • PL = Power delivered to load
  • PSUP = Power drawn from power supply
  • VLRMS = RMS voltage on BTL load
  • RL = Load resistance
  • VP = Peak voltage on BTL load

Therefore, PL is calculated by Equation 2:

Equation 2. SLOS490TPA6205A1 eq_11_slos490.gif

And PSUP is calculated by Equation 3:

Equation 3. SLOS490TPA6205A1 eq_12_slos490.gif

where

  • PSUP = Power drawn from power supply
  • IDDavg = Average current drawn from the power supply
  • VDD = Power supply voltage

IDDavg can be found in Equation 4:

Equation 4. SLOS490TPA6205A1 eq_13_slos490.gif

Therefore PSUP is calculated by Equation 5:

Equation 5. SLOS490TPA6205A1 eq_14_slos490.gif

substituting PL and PSUP into Equation 6,

Equation 6. SLOS490TPA6205A1 eq_15_slos490.gif

where

  • SLOS490TPA6205A1 eq_16_slos490.gif

Therefore:

Equation 7. SLOS490TPA6205A1 eq_17_slos490.gif

where

  • ηBTL = Efficiency of a BTL amplifier

Table 2. Efficiency and Maximum Ambient Temperature vs Output Power in 5-V 8- Ω BTL Systems

OUTPUT POWER (W) EFFICIENCY (%) INTERNAL DISSIPATION (W) POWER FROM SUPPLY (W) MAX AMBIENT TEMPERATURE (°C)
0.25 31.4 0.55 0.75 62
0.5 44.4 0.62 1.12 54
1 62.8 0.59 1.59 58
1.25 70.2 0.53 1.78 65

Table 2 employs Equation 7 to calculate efficiencies for four different output power levels. Note that the efficiency of the amplifier is quite low for lower power levels and rises sharply as power to the load is increased resulting in a nearly flat internal power dissipation over the normal operating range. Note that the internal dissipation at full output power is less than in the half power range. Calculating the efficiency for a specific system is the key to proper power supply design. For a 1.25-W audio system with 8-Ω loads and a 5-V supply, the maximum draw on the power supply is almost 1.8 W.

A final point to remember about Class-AB amplifiers is how to manipulate the terms in the efficiency equation to the utmost advantage when possible. Note that in Equation 7, VDD is in the denominator. This indicates that as VDD goes down, efficiency goes up.

Equation 8 is a simple formula for calculating the maximum power dissipated, PDmax, may be used for a differential output application:

Equation 8. SLOS490TPA6205A1 eq_18_slos490.gif

PDmax for a 5-V, 8-Ω system is 634 mW.

The maximum ambient temperature depends on the heat sinking ability of the PCB system. The derating factor for the 2 mm × 2 mm Microstar Junior package is shown in the dissipation rating table. Converting this to θJA is shown in Equation 9:

Equation 9. SLOS490TPA6205A1 eq_19_slos490.gif

Given θJA, the maximum allowable junction temperature, and the maximum internal dissipation, the maximum ambient temperature can be calculated with Equation 10. The maximum recommended junction temperature for the TPA6205A1 is 125°C.

Equation 10. SLOS490TPA6205A1 eq_20_slos490.gif

Equation 10 shows that the maximum ambient temperature is 53.3°C at maximum power dissipation with a 5-V supply. Table 2 shows that for most applications no airflow is required to keep junction temperatures in the specified range. The TPA6205A1 is designed with thermal protection that turns the device off when the junction temperature surpasses 150°C to prevent damage to the IC. Also, using more resistive than 8-Ω packages, it is good practice minimize the speakers dramatically increases the thermal performance by reducing the output current.

9.3.3 Differential Output Versus Single-Ended Output

Figure 28 shows a Class-AB audio power amplifier (APA) in a fully differential configuration. The TPA6205A1 amplifier has differential outputs driving both ends of the load. There are several potential benefits to this differential drive configuration, but initially consider power to the load. The differential drive to the speaker means that as one side is slewing up, the other side is slewing down, and vice versa. This in effect doubles the voltage swing on the load as compared to a ground referenced load. Plugging 2 × VO(PP) into the power equation, where voltage is squared, yields 4× the output power from the same supply rail and load impedance (see Equation 11).

Equation 11. SLOS490TPA6205A1 eq_06_slos490.gif
SLOS490TPA6205A1 sc_02_diff_outp_config_slos490.gif Figure 28. Differential Output Configuration

In a typical wireless handset operating at 3.6 V, bridging raises the power into an 8-Ω speaker from a singled-ended (SE, ground reference) limit of 200 mW to 800 mW. In sound power that is a 6-dB improvement—which is loudness that can be heard. In addition to increased power there are frequency response concerns. Consider the single-supply SE configuration shown in Figure 29. A coupling capacitor is required to block the DC offset voltage from reaching the load. This capacitor can be quite large (approximately 33 μF to 1000 μF) so it tends to be expensive, heavy, occupy valuable PCB area, and have the additional drawback of limiting low-frequency performance of the system. This frequency-limiting effect is due to the high pass filter network created with the speaker impedance and the coupling capacitance and is calculated with Equation 12.

Equation 12. SLOS490TPA6205A1 eq_07_slos490.gif

For example, a 68-μF capacitor with an 8-Ω speaker would attenuate low frequencies below 293 Hz. The BTL configuration cancels the DC offsets, which eliminates the need for the blocking capacitors. Low-frequency performance is then limited only by the input network and speaker response. Cost and PCB space are also minimized by eliminating the bulky coupling capacitor.

SLOS490TPA6205A1 sc_03_sngl_end_outp_freq_respns_slos490.gif Figure 29. Single-Ended Output and Frequency Response

Increasing power to the load does carry a penalty of increased internal power dissipation. The increased dissipation is understandable considering that the BTL configuration produces 4× the output power of the SE configuration.

9.4 Device Functional Modes

9.4.1 Summing Input Signals With The TPA6205A1

Most wireless phones or PDAs need to sum signals at the audio power amplifier or just have two signal sources that need separate gain. The TPA6205A1 makes it easy to sum signals or use separate signal sources with different gains. Many phones now use the same speaker for the earpiece and ringer, where the wireless phone would require a much lower gain for the phone earpiece than for the ringer. PDAs and phones that have stereo headphones require summing of the right and left channels to output the stereo signal to the mono speaker.

9.4.1.1 Summing Two Differential Input Signals

Two extra resistors are needed for summing differential signals (a total of 10 components). The gain for each input source can be set independently (see Equation 13 and Equation 14, and Figure 30).

Equation 13. SLOS490TPA6205A1 eq_04_slos490.gif
Equation 14. SLOS490TPA6205A1 eq_05_slos490.gif
SLOS490TPA6205A1 app_schem_04_tpa6205a1_summing_2_diff_inp_slos490.gif Figure 30. Application Schematic With TPA6205A1 Summing Two Differential Inputs

9.4.1.2 Summing a Differential Input Signal and a Single-Ended Input Signal

Figure 31 shows how to sum a differential input signal and a single-ended input signal. Ground noise can couple in through IN+ with this method. It is better to use differential inputs. To assure that each input is balanced, the single-ended input must be driven by a low-impedance source even if the input is not in use. Both input nodes must see the same impedance for optimum performance, thus the use of RP and CP.

Equation 15. SLOS490TPA6205A1 eq_04_slos490.gif
Equation 16. SLOS490TPA6205A1 eq_05_slos490.gif

9.4.1.3 Summing Two Single-Ended Input Signals

Four resistors and three capacitors are needed for summing single-ended input signals. The gain and corner frequencies (fc1 and fc2) for each input source can be set independently. Resistor, RP, and capacitor, CP, are needed on the IN+ terminal to match the impedance on the IN- terminal. The single-ended inputs must be driven by low impedance sources even if one of the inputs is not outputting an AC signal.

Equation 17. SLOS490TPA6205A1 eq_1_SNOS490.gif
Equation 18. SLOS490TPA6205A1 eq_2_SNOS490.gif
Equation 19. SLOS490TPA6205A1 eq_3_SNOS490.gif
Equation 20. SLOS490TPA6205A1 eq_4_SNOS490.gif
Equation 21. SLOS490TPA6205A1 eq_5_SNOS490.gif
Equation 22. SLOS490TPA6205A1 eq_6_SNOS490.gif
SLOS490TPA6205A1 app_schem_05_tpa6205a1_summing_2_sngl_end_inp_slos490.gif Figure 31. Application Schematic With TPA6205A1 Summing Two Single-Ended Inputs

9.4.2 Shutdown Mode

The TPA6205A1 can be put in shutdown mode when asserting SHUTDOWN pin to a logic LOW. While in shutdown mode, the device output stage is turned off, making the current consumption very low. The device exits shutdown mode when a HIGH logic level is applied to SHUTDOWN pin. SHUTDOWN pin is 1.8-V compatible.