SLOS490C July   2006  – November 2015

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Operating Characteristics
    7. 7.7 Dissipation Ratings
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Fully Differential Amplifiers
        1. 9.3.1.1 Advantages of Fully Differential Amplifiers
      2. 9.3.2 Fully Differential Amplifier Efficiency and Thermal Information
      3. 9.3.3 Differential Output Versus Single-Ended Output
    4. 9.4 Device Functional Modes
      1. 9.4.1 Summing Input Signals With The TPA6205A1
        1. 9.4.1.1 Summing Two Differential Input Signals
        2. 9.4.1.2 Summing a Differential Input Signal and a Single-Ended Input Signal
        3. 9.4.1.3 Summing Two Single-Ended Input Signals
      2. 9.4.2 Shutdown Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 TPA6205A1 With Differential Input
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Selecting Components
            1. 10.2.1.2.1.1 Resistors (RF and RI)
            2. 10.2.1.2.1.2 Bypass Capacitor (CBYPASS) and Start-Up Time
            3. 10.2.1.2.1.3 Input Capacitor (CI)
            4. 10.2.1.2.1.4 Decoupling Capacitor (CS)
          2. 10.2.1.2.2 Using Low-ESR Capacitors
        3. 10.2.1.3 Application Curves
      2. 10.2.2 TPA6205A1 With Differential Input and Input Capacitors
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curves
      3. 10.2.3 TPA6205A1 With Single-Ended Input
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
        3. 10.2.3.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Power Supply Decoupling Capacitors
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Community Resources
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VDD Supply voltage –0.3 6 V
VI Input voltage INx and SHUTDOWN pins –0.3 0.3 V
Continuous total power dissipation See Dissipation Ratings
TA Operating free-air temperature –40 85 ºC
TJ Junction temperature –40 125 ºC
Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds ZQV, DRB, DGN 260 ºC
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDD Supply voltage 2.5 5.5 V
VIH High-level input voltage SHUTDOWN 1.15 V
VIL Low-level input voltage SHUTDOWN 0.5 V
VIC Common-mode input voltage VDD = 2.5 V, 5.5 V, CMRR ≤ –60 dB 0.5 VDD–0.8 V
TA Operating free-air temperature –40 85 °C
ZL Load impedance 6.4 8 Ω

7.4 Thermal Information

THERMAL METRIC(1) TPA6205A1 UNIT
BGA MICROSTAR JUNIOR SON MSOP PowerPAD
8 PINS 8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 134.4 57.3 109.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 79.8 84.0 67.8 °C/W
RθJB Junction-to-board thermal resistance 71.1 32.2 47.6 °C/W
ψJT Junction-to-top characterization parameter 5.3 3.7 4.7 °C/W
ψJB Junction-to-board characterization parameter 71.0 32.2 47.2 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — 11.8 15.9 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
[VOO] Output offset voltage (measured differentially) VI = 0 V, VDD = 2.5 V to 5.5 V 9 mV
PSRR Power supply rejection ratio VDD = 2.5 V to 5.5 V –90 –70 dB
CMRR Common-mode rejection ratio VDD = 3.6 V to 5.5 V, VIC = 0.5 V to VDD – 0.8 –70 –65 dB
VDD = 2.5 V, VIC = 0.5 V to 1.7 V –62 –55
VOL Low-level output voltage RL = 8 Ω, VIN+ = VDD, VIN– = 0 V or VIN+ = 0 V, VIN– = VDD VDD = 5.5 V 0.3 0.46 V
VDD = 3.6 V 0.22
VDD = 2.5 V 0.19 0.26
VOH High-level output voltage RL = 8 Ω, VIN+ = VDD, VIN– = 0 V or VIN+ = 0 V, VIN– = VDD VDD = 5.5 V 4.8 5.12 V
VDD = 3.6 V 3.28
VDD = 2.5 V 2.1 2.24
[IIH] High-level input current VDD = 5.5 V, VI = 5.8 V 1.2 µA
[IIL] Low-level input current VDD = 5.5 V, VI = –0.3 V 1.2 µA
IDD Supply current VDD = 2.5 V to 5.5 V, No load, SHUTDOWN = VIH 1.7 2 mA
IDD(SD) Supply current in shutdown mode SHUTDOWN = VIL , VDD = 2.5 V to 5.5 V, No load 0.01 0.9 µA

7.6 Operating Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PO Output power THD + N = 1%, f = 1 kHz VDD = 5 V 1.25 W
VDD = 3.6 V 0.63
VDD = 2.5 V 0.3
THD+N Total harmonic distortion plus noise VDD = 5 V, PO = 1 W, f = 1 kHz 0.06%
VDD = 3.6 V, PO = 0.5 W, f = 1 kHz 0.07%
VDD = 2.5 V, PO = 200 mW, f = 1 kHz 0.08%
kSVR Supply ripple rejection ratio C(BYPASS) = 0.47°F, VDD = 3.6 V to 5.5 V, Inputs AC-grounded with CI = 2 F f = 217 Hz to 2 kHz, VRIPPLE = 200 mVPP –87 dB
C(BYPASS) = 0.47 F, VDD = 2.5 V to 3.6 V, Inputs AC-grounded with CI = 2 F f = 217 Hz to 2 kHz, VRIPPLE = 200 mVPP –82
C(BYPASS) = 0.47 F, VDD = 2.5 V to 5.5 V, Inputs AC-grounded with CI = 2 F f = 40 Hz to 20 kHz, VRIPPLE = 200 mVPP ≤ –74
SNR Signal-to-noise ratio VDD = 5 V, PO= 1 W 104 dB
Vn Output voltage noise f = 20 Hz to 20 kHz No weighting 17 VRMS
A weighting 13
CMRR Common-mode rejection ratio VDD= 2.5 V to 5.5 V, Resistor tolerance = 0.1%, Gain = 4V/V, VICM = 200 mVPP f = 20 Hz to 1 kHz ≤ –85 dB
f = 20 Hz to 20 kHz ≤ –74
ZI Input impedance 2 MΩ
ZO Output impedance Shutdown mode >10 kΩ
Shutdown attenuation f = 20 Hz to 20 kHz, RF = RI = 20 kΩ –80 dB

7.7 Dissipation Ratings

PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR TA ≤ 70°C POWER RATING TA ≤ 85°C POWER RATING
ZQV 885 mW 8.8 mW/°C 486 mW 354 mW
DGN 2.13 W 17.1 mW/°C 1.36 W 1.11 W
DRB 2.7 W 21.8 mW/°C 1.7 W 1.4 W

7.8 Typical Characteristics

Table 1. Table of Graphs

FIGURE
PO Output power vs Supply voltage Figure 1
vs Load resistance Figure 2, Figure 3
PD Power dissipation vs Output power Figure 4, Figure 5
Maximum ambient temperature vs Power dissipation Figure 6
Total harmonic distortion + noise vs Output power Figure 7, Figure 8
vs Frequency Figure 9, Figure 10, Figure 11, Figure 12
vs Common-mode input voltage Figure 13
Supply voltage rejection ratio vs Frequency Figure 14, Figure 15, Figure 16, Figure 17
Supply voltage rejection ratio vs Common-mode input voltage Figure 18
GSM Power supply rejection vs Time Figure 19
GSM Power supply rejection vs Frequency Figure 20
CMRR Common-mode rejection ratio vs Frequency Figure 21
vs Common-mode input voltage Figure 22
Closed loop gain/phase vs Frequency Figure 23
Open loop gain/phase vs Frequency Figure 24
IDD Supply current vs Supply voltage Figure 25
Start-up time vs Bypass capacitor Figure 26
SLOS490TPA6205A1 tc_01_op_vs_sv_slos490.gif
Figure 1. Output Power vs Supply Voltage
SLOS490TPA6205A1 tc_03_op_vs_lr_slos490.gif
Figure 3. Output Power vs Load Resistance
SLOS490TPA6205A1 tc_05_pd_vs_op_slos490.gif
Figure 5. Power Dissipation vs Output Power
SLOS490TPA6205A1 tc_07_thdn_vs_op_slos490.gif
Figure 7. Total Harmonic Distortion + Noise vs Output Power
SLOS490TPA6205A1 tc_09_thdn_vs_freq_slos490.gif
Figure 9. Total Harmonic Distortion + Noise vs Frequency
SLOS490TPA6205A1 tc_11_thdn_vs_freq_slos490.gif
Figure 11. Total Harmonic Distortion + Noise vs Frequency
SLOS490TPA6205A1 tc_13_thdn_vs_cmiv_slos490.gif
Figure 13. Total Harmonic Distortion + Noise vs Common-Mode Input Voltage
SLOS490TPA6205A1 tc_15_svrr_vs_freq_slos490.gif
Figure 15. Supply Voltage Rejection Ratio vs Frequency
SLOS490TPA6205A1 tc_17_svrr_vs_freq_slos490.gif
Figure 17. Supply Voltage Rejection Ratio vs Frequency
SLOS490TPA6205A1 tc_19_gpsr_vs_time_slos490.gif
Figure 19. GSM Power Supply Rejection vs Time
SLOS490TPA6205A1 tc_21_cmrr_vs_freq_slos490.gif
Figure 21. Common-Mode Rejection Ratio vs Frequency
SLOS490TPA6205A1 tc_23_clgp_vs_freq_slos490.gif
Figure 23. Closed-Loop Gain / Phase vs Frequency
SLOS490TPA6205A1 tc_25_sc_vs_sv_slos490.gif
Figure 25. Supply Current vs Supply Voltage
SLOS490TPA6205A1 tc_02_op_vs_lr_slos490.gif
Figure 2. Output Power vs Load Resistance
SLOS490TPA6205A1 tc_04_pd_vs_op_slos490.gif
Figure 4. Power Dissipation vs Output Power
SLOS490TPA6205A1 tc_06_mat_vs_pd_slos490.gif
Figure 6. Maximum Ambient Temperature vs Power Dissipation
SLOS490TPA6205A1 tc_08_thdn_vs_op_slos490.gif
Figure 8. Total Harmonic Distortion + Noise vs Output Power
SLOS490TPA6205A1 tc_10_thdn_vs_freq_slos490.gif
Figure 10. Total Harmonic Distortion + Noise vs Frequency
SLOS490TPA6205A1 tc_12_thdn_vs_freq_slos490.gif
Figure 12. Total Harmonic Distortion + Noise vs Frequency
SLOS490TPA6205A1 tc_14_svrr_vs_freq_slos490.gif
Figure 14. Supply Voltage Rejection Ratio vs Frequency
SLOS490TPA6205A1 tc_16_svrr_vs_freq_slos490.gif
Figure 16. Supply Voltage Rejection Ratio vs Frequency
SLOS490TPA6205A1 tc_18_svrr_vs_freq_slos490.gif
Figure 18. Supply Voltage Rejection Ratio vs Common-Mode Input Voltage
SLOS490TPA6205A1 tc_20_gpsr_vs_freq_slos490.gif
Figure 20. GSM Power Supply Rejection vs Frequency
SLOS490TPA6205A1 tc_22_cmrr_vs_cmiv_slos490.gif
Figure 22. Common-Mode Rejection Ratio vs Common-Mode Input Voltage
SLOS490TPA6205A1 tc_24_olgp_vs_freq_slos490.gif
Figure 24. Open-Loop Gain / Phase vs Frequency
SLOS490TPA6205A1 tc_26_sut_vs_bc_slos490.gif
Start-Up time is the time it takes (from a low-to-high transition on SHUTDOWN) for the gain of the amplifier to reach –3 dB of the final gain
Figure 26. Start-Up Time vs Bypass Capacitor