SLASEP6B September   2019  – December 2020 TPA6304-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
      1. 6.6.1 Bridge-Tied Load (BTL), BD
      2. 6.6.2 Parallel Bridge-Tied Load (PBTL)
      3. 6.6.3 Bridge-Tied Load (BTL), 1SPW
      4. 6.6.4 Bridge-Tied Load (BTL), 384 kHz, BD
      5. 6.6.5 Bridge-Tied Load (BTL), 384 kHz, 1SPW
  7. 7 Parameter measurement information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Single-Ended Analog Inputs
      2. 7.3.2  Gain Control
      3. 7.3.3  Class-D Operation and Spread Spectrum Control
        1. 7.3.3.1 High Frequency Pulse Width Modulator (PWM)
        2. 7.3.3.2 Clock Synchronization
        3. 7.3.3.3 Spread Spectrum Control
      4. 7.3.4  Gate Drive
      5. 7.3.5  Power FETs
      6. 7.3.6  Load Diagnostics
        1. 7.3.6.1 DC Load Diagnostics
          1. 7.3.6.1.1 Automatic DC Load Diagnostics at Device Initialization
          2. 7.3.6.1.2 Automatic DC Load Diagnostics During Hi-Z to MUTE or PLAY Transition
          3. 7.3.6.1.3 Manual Start of DC Load Diagnostics
          4. 7.3.6.1.4 Short-to-Ground
          5. 7.3.6.1.5 Short-to-Power
          6. 7.3.6.1.6 Shorted Load and Open Load
          7. 7.3.6.1.7 Line Output Diagnostics
        2. 7.3.6.2 AC Load Diagnostics
          1. 7.3.6.2.1 Operating Principal
          2. 7.3.6.2.2 Stimulus
          3. 7.3.6.2.3 Load Impedance
          4. 7.3.6.2.4 Tweeter Detection
          5. 7.3.6.2.5 Operation
      7. 7.3.7  Power Supply
        1. 7.3.7.1 Power-Supply Sequence
          1. 7.3.7.1.1 Power-Up Sequence
          2. 7.3.7.1.2 Power-Down Sequence
      8. 7.3.8  Device Initialization and Power-On-Reset (POR)
      9. 7.3.9  Protection and Monitoring
        1. 7.3.9.1 Over Current Protection
        2. 7.3.9.2 DC Detect
        3. 7.3.9.3 Load Current Limit
        4. 7.3.9.4 Clip Detect
        5. 7.3.9.5 Temperature Protection and Monitoring
          1. 7.3.9.5.1 Over Temperature Shutdown (OTSD)
          2. 7.3.9.5.2 Over Temperature Warning (OTW)
          3. 7.3.9.5.3 Thermal Gain Foldback (TGFB)
        6. 7.3.9.6 Power Failures
        7. 7.3.9.7 Load Dump Protection
      10. 7.3.10 Hardware Control Pins
        1. 7.3.10.1 FAULT Pin
        2. 7.3.10.2 STANDBY Pin
        3. 7.3.10.3 GPIO Pins
        4. 7.3.10.4 WARNING
        5. 7.3.10.5 MUTE
    4. 7.4 Device Functional Modes
      1. 7.4.1 Internal Reporting Signals
        1. 7.4.1.1 Fault Signal
        2. 7.4.1.2 Warning Signal
        3. 7.4.1.3 Clip Detect Signal
      2. 7.4.2 Device States and Flags
        1. 7.4.2.1 Audio Channel States
          1. 7.4.2.1.1 PROTECTIVE SHUTDOWN with AUTO RECOVERY State
          2. 7.4.2.1.2 PROTECTIVE SHUTDOWN State
            1. 7.4.2.1.2.1 Clear Fault
        2. 7.4.2.2 Status and Memory Registers
          1. 7.4.2.2.1 Status Registers
          2. 7.4.2.2.2 Memory Registers
      3. 7.4.3 Fault Events
        1. 7.4.3.1 Overview
        2. 7.4.3.2 Power Fault Events
          1. 7.4.3.2.1 DVDD POR
          2. 7.4.3.2.2 VBAT Over Voltage Fault
          3. 7.4.3.2.3 VBAT Under Voltage Fault
          4. 7.4.3.2.4 PVDD Over Voltage Fault
          5. 7.4.3.2.5 PVDD Under Voltage Fault
          6. 7.4.3.2.6 GVDD Fault
        3. 7.4.3.3 Over Temperature Shut Down (OTSD) Event
        4. 7.4.3.4 Over Current Shut Down (OCSD) Event
        5. 7.4.3.5 DC Fault Event
        6. 7.4.3.6 Load Current Fault Event
        7. 7.4.3.7 Invalid Clock Fault Event
      4. 7.4.4 Warning Events
        1. 7.4.4.1 Overview
        2. 7.4.4.2 Over Temperature Warning Event
        3. 7.4.4.3 Thermal Gain Foldback Warning Event
        4. 7.4.4.4 Load Current Warning Event
        5. 7.4.4.5 Clip Warning Event
    5. 7.5 Programming
      1. 7.5.1 I2C Serial Communication Bus
        1. 7.5.1.1 I2C Address Selection
      2. 7.5.2 I2C Bus Protocol
        1. 7.5.2.1 Random Write
        2. 7.5.2.2 Sequential Write
        3. 7.5.2.3 Random Read
        4. 7.5.2.4 Sequential Read
    6. 7.6 Register Maps
      1. 7.6.1 Registers
  9. 8 Application Information Disclaimer
    1. 8.1 Application Information
      1. 8.1.1 AM Radio Avoidance
      2. 8.1.2 Parallel BTL Operation (PBTL)
      3. 8.1.3 Reconstruction Filter Design
      4. 8.1.4 Bootstrap Capacitors
      5. 8.1.5 Line Driver Applications
    2. 8.2 Typical Applications
      1. 8.2.1 BTL Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Hardware Design Procedure
      2. 8.2.2 PBTL Application
        1. 8.2.2.1 Detailed Hardware Design Procedure
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Electrical Connection of Thermal Pad and Heat Sink
      2. 10.1.2 General Considerations
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-20200925-CA0I-6W6Z-JXLX-PBM757Q0ZGPT-low.gif Figure 5-1 DDV Package, 44-Pin HTSSOP, Top View
Table 5-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
AVDD 6 PWR Voltage regulator bypass, derived from VBAT input pins. Connect 1 µF capacitor from AVDD (pin 6) to AVDD_RET (pin 7).
AVDD_RET 7 GND AVDD voltage regulator return. Connect to ground.
BST_1M 23 PWR Bootstrap capacitor connection pins for high-side gate driver
BST_1P 27 PWR Bootstrap capacitor connection pins for high-side gate driver
BST_2M 28 PWR Bootstrap capacitor connection pins for high-side gate driver
BST_2P 32 PWR Bootstrap capacitor connection pins for high-side gate driver
BST_3M 35 PWR Bootstrap capacitor connection pins for high-side gate driver
BST_3P 39 PWR Bootstrap capacitor connection pins for high-side gate driver
BST_4M 40 PWR Bootstrap capacitor connection pins for high-side gate driver
BST_4P 44 PWR Bootstrap capacitor connection pins for high-side gate driver
DVDD 14 PWR DVDD supply input. Connect 1 µF capacitor from DVDD to DVSS (pin 13).
DVSS 13 GND DVDD ground reference. Connect to ground.
FAULT 18 DI/O Reports a fault (active low, open drain), external pullup resistor determines I2C address during power on reset.
GND 21, 25, 30, 37, 42 GND Ground
GPIO1 19 DI/O General purpose IO, function set by register programming.
GPIO2 20 DI/O General purpose IO, function set by register programming.
GVDD 5 PWR Gate drive voltage regulator bypass for all output channels, derived from VBAT input pins. Connect 2.2µF capacitor to GVDD_RET (pin 4).
GVDD_RET 4 GND Gate drive voltage regulator return. Connect to ground.
IN_1 12 AI Non-inverting input channel. Internally biased to AVDD/2. Connect to AC coupling capacitor.
IN_2 11 AI Non-inverting input channel. Internally biased to AVDD/2. Connect to AC coupling capacitor.
IN_3 10 AI Non-inverting input channel. Internally biased to AVDD/2. Connect to AC coupling capacitor.
IN_4 9 AI Non-inverting input channel. Internally biased to AVDD/2. Connect to AC coupling capacitor.
IN_REF 8 AI Reference input voltage for IN_1, IN_2, IN_3, IN_4. Internally biased to AVDD/2. Connect to AC coupling capacitor.
OUT_1M 24 NO Negative output for the channel
OUT_1P 26 PO Positive output for the channel
OUT_2M 29 NO Negative output for the channel
OUT_2P 31 PO Positive output for the channel
OUT_3M 36 NO Negative output for the channel
OUT_3P 38 PO Positive output for the channel
OUT_4M 41 NO Negative output for the channel
OUT_4P 43 PO Positive output for the channel
PVDD 1, 22, 33, 34 PWR PVDD voltage input carrying load currents (can be connected to battery).
PVDDQ 2 PWR PVDD voltage input not loaded with load currents (can be connected to battery).
SCL 15 DI I2C clock input
SDA 16 DI/O I2C data input and output
STANDBY 17 DI Enables low power standby state (active Low), 100-kΩ internal pulldown resistor.
VBAT 3 PWR Battery voltage input
Thermal Pad — GND Provides thermal connection for the device. Heatsink must be connected to GND.
(1) AI = analog input, GND = ground, PWR = power, PO = positive output, NO = negative output, DI = digital input, DO = digital output,
DI/O = digital input and output, NC = No Connection