Refer to the PDF data sheet for device specific package drawings
The TPA6404-Q1 device is a four-channel analog-input Class-D audio amplifier that implements a 2.1MHz PWM switching frequency that enables a cost optimized solution in a very small 4.5cm2 PCB size, full operation down to 4.5V for start/stop events, and exceptional sound quality with up to 100kHz audio bandwidth.
The TPA6404-Q1 Class-D audio amplifier has an optimal design for use in entry level automotive head units that provide analog audio input signals as part of their system design.
The Class-D topology dramatically improves efficiency over traditional linear amplifier solutions.
The output switching frequency operates above the AM band, which eliminates the AM band interference and reduces the output filter size and cost.
The device is offered in a 56 pin HSSOP package with the exposed thermal pad up.
PART NUMBER | PACKAGE(1) | BODY SIZE (NOM) |
---|---|---|
TPA6404-Q1 | HSSOP (56) | 18.41mm × 7.49mm |
PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
AVDD | 5 | PWR | Voltage regulator bypass. Connect 1µF capacitor from AVDD to AVSS |
AVSS | 4 | PWR | AVDD bypass capacitor return |
BST_1M | 31 | PWR | Bootstrap capacitor connection pins for high-side gate driver |
BST_1P | 35 | PWR | Bootstrap capacitor connection pins for high-side gate driver |
BST_2M | 37 | PWR | Bootstrap capacitor connection pins for high-side gate driver |
BST_2P | 41 | PWR | Bootstrap capacitor connection pins for high-side gate driver |
BST_3M | 44 | PWR | Bootstrap capacitor connection pins for high-side gate driver |
BST_3P | 48 | PWR | Bootstrap capacitor connection pins for high-side gate driver |
BST_4M | 50 | PWR | Bootstrap capacitor connection pins for high-side gate driver |
BST_4P | 54 | PWR | Bootstrap capacitor connection pins for high-side gate driver |
DVDD | 18 | PWR | DVDD supply input. Connect 1 µF capacitor from DVDD to DVSS |
DVSS | 17 | GND | DVDD Ground Reference |
FAULT | 26 | DO | Reports a fault (active low, open drain), 100-kΩ internal pull-up resistor |
GND | 1, 8, 28, 33, 36, 39, 46, 49, 52 | GND | Ground |
GVDD_34 | 6 | PWR | Gate drive voltage regulator for channel 3 and 4, derived from VBAT input pins. Connect 2.2µF capacitor to GND |
GVDD_12 | 7 | PWR | Gate drive voltage regulator for channel 1 and 2, derived from VBAT input pins. Connect 2.2µF capacitor to GND |
I2C_ADDR0 | 22 | DI | I2C address pins. Refer to Table 7-7 |
I2C_ADDR1 | 23 | ||
IN_1M | 16 | AI | Negative input for the channel |
IN_1P | 15 | AI | Positive input for the channel |
IN_2M | 14 | AI | Negative input for the channel |
IN_2P | 13 | AI | Positive input for the channel |
IN_3M | 12 | AI | Negative input for the channel |
IN_3P | 11 | AI | Positive input for the channel |
IN_4M | 10 | AI | Negative input for the channel |
IN_4P | 9 | AI | Positive input for the channel |
MUTE | 25 | DI | Mutes the device outputs (active low), 100-kΩ internal pull-down resistor |
OUT_1M | 32 | NO | Negative output for the channel |
OUT_1P | 34 | PO | Positive output for the channel |
OUT_2M | 38 | NO | Negative output for the channel |
OUT_2P | 40 | PO | Positive output for the channel |
OUT_3M | 45 | NO | Negative output for the channel |
OUT_3P | 47 | PO | Positive output for the channel |
OUT_4M | 51 | NO | Negative output for the channel |
OUT_4P | 53 | PO | Positive output for the channel |
PVDD | 2, 29, 30, 42, 43, 55, 56 | PWR | PVDD voltage input (can be connected to battery) |
SCL | 20 | DI | I2C clock input |
SDA | 21 | DI/O | I2C data input and output |
STANDBY | 24 | DI | Enables low power standby state (active Low), 1MΩ internal pull-down resistor |
SYNC | 19 | DI/O | Sync clock input or output |
VBAT | 3 | PWR | Battery voltage input |
WARN | 27 | DO | Clip and overtemperature warning (active low, open drain), 100kΩ internal pull-up resistor |
Thermal Pad | — | GND | Provides both electrical and thermal connection for the device. Heatsink must be connected to GND. |