The TPD12S015 device is an integrated HDMI ESD solution. The device pin mapping matches the HDMI Type C and Type D connector with four differential pairs. This device offers eight low-capacitance ESD clamps, allowing HDMI 1.3 or 1.4 data rates. The integrated ESD clamps and resistors provide good matching between each differential signal pair, which allows an advantage over discrete ESD clamp solutions where variations between ESD clamps degrade the differential signal quality.
The TPD12S015 provides a regulated 5-V output (5VOUT) for sourcing the HDMI power line. The regulated 5-V output supplies up to 55 mA to the HDMI receiver. The control of 5VOUT and the hot plug detect (HPD) circuitry is independent of the LS_OE control signal and is controlled by the CT_CP_HPD pin. This independent control enables the detection scheme (5VOUT + HPD) to be active before enabling the HDMI link.
There are three noninverting, bidirectional translation circuits for the SDA, SCL, and CEC lines. Each have a common power rail (VCCA) on the A side from 1.1 V to 3.6 V . On the B side, the SCL_B and SDA_B each have an internal 1.75-kΩ pullup connected to the regulated 5-V rail (5VOUT). The SCL and SDA pins meet the I2C specification and drive up to 750-pF loads. The CEC_B pin has an internal 27-kΩ pullup to an internal 3.3-V supply.
The HPD_B port has a glitch filter to avoid false detection due to the bouncing while inserting the HDMI plug.
The TPD12S015 provides IEC61000-4-2 (Level 4) ESD protection. This device is offered in a space-saving 1.6-mm × 2.8-mm wafer-level chip scale package [DSBGA (YFF)] with a 0.4-mm pitch.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPD12S015 | DSBGA (28) | 1.56 mm × 2.76 mm |
Changes from E Revision (June 2013) to F Revision
Changes from D Revision (April 2012) to E Revision
Changes from C Revision (November 2010) to D Revision
Changes from B Revision (July 2010) to C Revision
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
5VOUT | F1 | Pwr O | DC-DC output. The 5-V power pin can supply 55-mA regulated current to the HDMI receiver. Separate DC-DC converter control pin CT_CP_HPD disables the DC-DC converter when operating at low-power mode. |
CEC_A | B2 | I/O | System-side CEC bus I/O. This pin is bidirectional and referenced to VCCA. |
CEC_B | D3 | I/O | HDMI-side CEC bus I/O. This pin is bidirectional and referenced to the 3.3-V internal supply. |
CLK– | G4 | ESD | High-speed ESD clamp: provides ESD protection to the high-speed HDMI differential data lines. |
CLK+ | F4 | ||
CT_CP_HPD | D1 | Ctrl | DC-DC Enable. Enables the DC-DC converter and HPD circuitry when CT_CP_HPD = H. The CT_CP_HPD is referenced to VCCA. |
D0– | E4 | ESD | High-speed ESD clamp: provides ESD protection to the high-speed HDMI differential data lines. |
D0+ | D4 | ||
D1– | C4 | ||
D1+ | B4 | ||
D2– | A4 | ||
D2+ | A3 | ||
FB | E1 | I | Feedback input. This pin is a feedback control pin for the DC-DC converter. It must be connected to 5VOUT. |
GND | B3, C3, D2, E2 |
— | Device ground |
HPD_A | C2 | O | System-side output for the hot plug detect. This pin is unidirectional and is referenced to VCCA. |
HPD_B | G3 | I | HDMI-side input for the hot plug detect. This pin is unidirectional and is referenced to 5VOUT. |
LS_OE | A1 | Ctrl | Level shifter enable. This pin is referenced to VCCA. Enables level shifters and LDO when OE = H. |
PGND | G1 | — | DC-DC converter ground. This pin should be tied externally to the system GND plane. See Layout Guidelines. |
SCL_A | B1 | I/O | System-side input and output for I2C bus. This pin is bidirectional and referenced to VCCA. |
SCL_B | E3 | I/O | HDMI-side input and output for I2C bus. This pin is bidirectional and referenced to 5VOUT. |
SDA_A | C1 | I/O | System-side input and output for I2C bus. This pin is bidirectional and referenced to VCCA. |
SDA_B | F3 | I/O | HDMI-side input and output for I2C bus. This pin is bidirectional and referenced to 5VOUT. |
SW | F2 | I | Switch input. This pin is the inductor input for the DC-DC converter. |
VBAT | G2 | Supply | Battery supply. This voltage is typically 2.3 V to 5.5 V. |
VCCA | A2 | Supply | System-side supply. This voltage is typically 1.2 V to 3.3 V from the core microcontroller. |
1 | 2 | 3 | 4 | |
---|---|---|---|---|
A | LS_OE | VCCA | D2+ | D2– |
B | SCL_A | CEC_A | GND | D1+ |
C | SDA_A | HPD_A | GND | D1– |
D | CT_CP_HPD | GND | CEC_B | D0+ |
E | FB | GND | SCL_B | D0– |
F | 5VOUT | SW | SDA_B | CLK+ |
G | PGND | VBAT | HPD_B | CLK– |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
VCCA | Supply voltage | 4 | V | ||
VBAT | Supply voltage | –0.3 | 6.5 | V | |
VI | Input voltage | SCL_A, SDA_A, CEC_A , CT_CP_HPD, LS_OE | –0.3 | 4 | V |
SCL_B, SDA_B, CEC_B, D, CLK | –0.3 | 6 | |||
VO | Voltage applied to any output in the high-impedance or power-off state(2) | SCL_A, SDA_A, CEC_A, HPD_A | –0.3 | 4 | V |
SCL_B, SDA_B, CEC_B | –0.3 | 6 | |||
Voltage applied to any output in the high or low state(2) | SCL_A, SDA_A, CEC_A, HPD_A | –0.3 | VCCA + 0.3 | ||
SCL_B, SDA_B, CEC_B | –0.5 | 6 | |||
IIK | Input clamp current | VI < 0 | –50 | mA | |
IOK | Output clamp current | VO < 0 | –50 | mA | |
IOUTMAX | Continuous current through 5VOUT or GND | ±100 | mA | ||
Tstg | Storage temperature | –65 | 150 | °C |
VALUE | UNIT | ||||
---|---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | All pins except E4, D4, C4, B4, A4, A3, G4, F4, D3, G3, E3, F3 F1, and E1 |
±2500 | V |
Pins E4, D4, C4, B4, A4, A3, G4, F4, D3, G3, E3, F3 F1, and E1 |
±15000 | ||||
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1000 | ||||
IEC 61000-4-2 contact discharge | Pins E4, D4, C4, B4, A4, A3, G4, F4, D3, G3, E3, F3 F1, and E1 |
±8000 |
THERMAL METRIC(1) | TPD12S015 | UNIT | |
---|---|---|---|
YFF (DSBGA) | |||
28 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 63 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 0.4 | °C/W |
RθJB | Junction-to-board thermal resistance | 9.2 | °C/W |
ψJT | Junction-to-top characterization parameter | 1.6 | °C/W |
ψJB | Junction-to-board characterization parameter | 9.1 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | N/A | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
ICCA | Standby | VCCA | I/O = High | 2 | µA | ||
Active | 15 | ||||||
ICCB | Standby | VBAT | CT_CP_HPD=L, LS_OE=L, HPD_B=L | 2 | µA | ||
DC-DC and HPD active | CT_CP_HPD=H, LS_OE=L, HPD_B=L | 30 | 50 | ||||
DC-DC, HPD, DDC, CEC active | CT_CP_HPD=H LS_OE=H, HPD_B=L, I/O =H | 225 | 300 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
IOFF | Current from IO port to supply pins | VCC = 0 V, VIO = 3.3 V | 0.01 | 0.5 | µA | ||
VDL | Diode forward voltage | ID = 8 mA, | Lower clamp diode | 0.85 | 1 | V | |
RDYN | Dynamic resistance | I = 1 A | D, CLK | 1 | Ω | ||
CIO | IO capacitance | VIO = 2.5 V | D, CLK | 1.3 | pF | ||
VBR | Break-down voltage | IIO = 1 mA | 9 | 12 | V |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VBAT | Input voltage range | 2.3 | 5.5 | V | ||
5VOUT | Total DC output voltage | Includes voltage references, DC load and line regulations, process and temperature | 4.9 | 5 | 5.13 | V |
TOVA | Total output voltage accuracy | Includes voltage references, DC load and line regulations, transient load and line regulations, ripple, process and temperature | 4.8 | 5 | 5.3 | V |
VO_Ripple | Output voltage ripple, loaded | IO = 65 mA | 20 | mVp-p | ||
F_clk | Internal operating frequency | VBAT = 2.3 V to 5.5 V | 3.5 | MHz | ||
tstart | Start-up time | From CT_CP_HPD input to 5-V power output 90% point | 300 | µs | ||
IO | Output current | VBAT = 2.3 V to 5.5 V | 55 | mA | ||
Reverse leakage current VO | CT_CP_HPD= L, VO = 5.5 V | 2.5 | µA | |||
Leakage current from battery to VO | CT_CP_HPD= L | 5 | µA | |||
VBATUV | Undervoltage lockout threshold | Falling | 2 | V | ||
Rising | 2.1 | |||||
VOVC | Input overvoltage threshold | Falling | 5.9 | V | ||
Rising | 6 | |||||
Line transient response | VBAT = 3.6 V, a pulse of 217-Hz 600 mVp-p square wave, IO = 20/65 mA | ±25 | ±50 | mVpk | ||
Load transient response | VBAT = 3.6 V, IO = 5 to 65 mA, pulse of 10 µs, tr = tf = 0.1 µs |
50 | mVpk | |||
IDD (idle) | Power supply current from VBAT to DC-DC, enabled, unloaded | IO = 0 mA | 30 | 50 | µA | |
IDD (disabled) | Power supply current from VBAT, DC-DC Disabled, Unloaded | VBAT = 2.3 V to 5.5 V, IO = 0 mA, CT_CP_HPD Low | 2 | µA | ||
IDD(system off) | Power supply current from VBAT, VCCA =0 V | VCCA = 0 V | 5 | µA | ||
I_inrush (start-up) | Inrush current, average over T_startup time | VBAT = 2.3 V to 5.5 V, IO = 65 mA | 100 | mA | ||
TSD | Thermal shutdown | Increasing junction temperature | 140 | °C | ||
Thermal shutdown hysteresis | Decreasing junction temperature | 20 | ||||
ISC | Short-circuit current limit from output | 5-Ω short to GND | 500 | mA |
PARAMETER | TYP | UNIT | |
---|---|---|---|
LIN | External inductor, 0805 footprint | 1 | µH |
CIN | Input capacitor, 0603 footprint | 4.7 | µF |
COUT | Output capacitor, 0603 footprint | 4.7 | µF |
CVCCA | Input capacitor, 0402 footprint | 0.1 | µF |
PARAMETER | TEST CONDITIONS | VCCA | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|---|
VOHA | IOH = –3 mA, | VI = VIH | 1.1 V to 3.6 V | VCCA × 0.7 | V | |||
VOLA | IOL = 3 mA, | VI = VIL | 1.1 V to 3.6 V | VCCA ×0.17 | V | |||
ΔVT hysteresis | HPD_B (VT+ – VT–) | 1.1 V to 3.6 V | 700 | mV | ||||
RPD | (Internal pulldown) | HPD_B, | Internal pulldown connected to GND | 11 | kΩ | |||
IOFF | A port | VO = VCCO or GND | 0 V | ±5 | µA | |||
IOZ | A port | VI = VCCI or GND | 3.6 V | ±5 | µA |
PARAMETER | TEST CONDITIONS | VCCA | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|---|
II | VI = VCCA or GND | 1.1 V to 3.6 V | ±12 | µA |
PARAMETER | TEST CONDITIONS | VCCA | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
CI | Control inputs | VI = 1.89 V or GND | 1.1 V to 3.6 V | 7.1 | 8.5 | pF | |
CIO | A port | VO = 1.89 V or GND | 1.1 V to 3.6 V | 8.3 | 9.5 | pF | |
B port | VO = 5.0 V or GND | 1.1 V to 3.6 V | 15 | 16.5 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
CL | Bus load capacitance (B side) | 750 | pF | |||
Bus load capacitance (A side) | 15 |
PARAMETER | PINS | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
tPHL | Propagation delay | A to B | DDC Channels Enabled | 344 | ns | ||
B to A | 335 | ||||||
tPLH | Propagation delay | A to B | DDC Channels Enabled | 452 | ns | ||
B to A | 178 | ||||||
tf | A port fall time | A Port | DDC Channels Enabled | 138 | ns | ||
B port fall time | B Port | 83 | |||||
tr | A port rise time | A Port | DDC Channels Enabled | 194 | ns | ||
B port rise time | B Port | 92 | |||||
fMAX | Maximum switching frequency | DDC Channels Enabled | 400 | kHz |
PARAMETER | PINS | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
tPLH | Propagation delay | A to B | CEC Channels Enabled | 445 | ns | ||
B to A | 337 | ||||||
tPLH | A to B | 13 | µs | ||||
B to A | 0.266 | ||||||
tf | A port fall time | A Port | CEC Channels Enabled | 140 | ns | ||
B port fall time | B Port | 96 | |||||
tr | A port rise time | A Port | CEC Channels Enabled | 202 | ns | ||
B port rise time | B Port | 15 | µs |
PARAMETER | PINS | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
tPLH | Propagation delay | B to A | CEC Channels Enabled | 10 | µs | ||
tPLH | B to A | 9 | |||||
tf | A port fall time | A Port | CEC Channels Enabled | 0.67 | ns | ||
tr | A port rise time | A Port | CEC Channels Enabled | 0.74 | ns |
PARAMETER | PINS | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
tPLH | Propagation delay | A to B | DDC Channels Enabled | 335 | ns | ||
B to A | 265 | ||||||
tPLH | A to B | 438 | |||||
B to A | 169 | ||||||
tf | A port fall time | A Port | DDC Channels Enabled | 110 | ns | ||
B port fall time | B Port | 83 | |||||
tr | A port rise time | A Port | DDC Channels Enabled | 190 | ns | ||
B port rise time | B Port | 92 | |||||
fMAX | Maximum switching frequency | DDC Channels Enabled | 400 | kHz |
PARAMETER | PINS | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
tPLH | Propagation delay | A to B | CEC Channels Enabled | 437 | ns | ||
B to A | 267 | ||||||
tPLH | A to B | 13 | µs | ||||
B to A | 0.264 | ||||||
tf | A port fall time | A Port | CEC Channels Enabled | 110 | ns | ||
B port fall time | B Port | 96 | |||||
tr | A port rise time | A Port | CEC Channels Enabled | 202 | ns | ||
B port rise time | B Port | 15 | µs |
PARAMETER | PINS | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
tPLH | Propagation delay | B to A | CEC Channels Enabled | 10 | µs | ||
tPLH | B to A | 9 | |||||
tf | A port fall time | A Port | CEC Channels Enabled | 0.47 | ns | ||
tr | A port rise time | A Port | CEC Channels Enabled | 0.51 | ns |
PARAMETER | PINS | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
tPLH | Propagation delay | A to B | DDC Channels Enabled | 334 | ns | ||
B to A | 229 | ||||||
tPLH | A to B | 431 | |||||
B to A | 169 | ||||||
tf | A port fall time | A Port | DDC Channels Enabled | 94 | ns | ||
B port fall time | B Port | 83 | |||||
tr | A port rise time | A Port | DDC Channels Enabled | 191 | ns | ||
B port rise time | B Port | 92 | |||||
fMAX | Maximum switching frequency | DDC Channels Enabled | 400 | kHz |
PARAMETER | PINS | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
tPLH | Propagation delay | A to B | CEC Channels Enabled | 441 | ns | ||
B to A | 231 | ||||||
tPLH | A to B | 13 | µs | ||||
B to A | 0.26 | ||||||
tf | A port fall time | A Port | CEC Channels Enabled | 94 | ns | ||
B port fall time | B Port | 96 | |||||
tr | A port rise time | A Port | CEC Channels Enabled | 201 | ns | ||
B port rise time | B Port | 15 | µs |
PARAMETER | PINS | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
tPLH | Propagation delay | B to A | CEC Channels Enabled | 10 | µs | ||
tPLH | B to A | 9 | |||||
tf | A port fall time | A Port | CEC Channels Enabled | 0.41 | ns | ||
tr | A port rise time | A Port | CEC Channels Enabled | 0.45 | ns |
PARAMETER | PINS | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
tPLH | Propagation delay | A to B | DDC Channels Enabled | 330 | ns | ||
B to A | 182 | ||||||
tPLH | A to B | 423 | |||||
B to A | 166 | ||||||
tf | A port fall time | A Port | DDC Channels Enabled | 79 | ns | ||
B port fall time | B Port | 83 | |||||
tr | A port rise time | A Port | DDC Channels Enabled | 188 | ns | ||
B port rise time | B Port | 92 | |||||
fMAX | Maximum switching frequency | DDC Channels Enabled | 400 | kHz |
PARAMETER | PINS | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
tPLH | Propagation delay | A to B | CEC Channels Enabled | 454 | ns | ||
B to A | 184 | ||||||
tPLH | A to B | 13 | µs | ||||
B to A | 0.255 | ||||||
tf | A port fall time | A Port | CEC Channels Enabled | 79 | ns | ||
B port fall time | B Port | 96 | |||||
tr | A port rise time | A Port | CEC Channels Enabled | 194 | ns | ||
B port rise time | B Port | 15 | µs |
PARAMETER | PINS | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
tPLH | Propagation delay | B to A | CEC Channels Enabled | 10 | µs | ||
tPLH | B to A | 9 | |||||
tf | A port fall time | A Port | CEC Channels Enabled | 0.37 | ns | ||
tr | A port rise time | A Port | CEC Channels Enabled | 0.39 | ns |
PARAMETER | PINS | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
tPLH | Propagation delay | A to B | DDC channels enabled | 323 | ns | ||
B to A | 158 | ||||||
tPLH | A to B | 421 | |||||
B to A | 162 | ||||||
tf | A port fall time | A Port | DDC channels enabled | 71 | ns | ||
B port fall time | B Port | 84 | |||||
tr | A port rise time | A Port | DDC channels enabled | 188 | ns | ||
B port rise time | B Port | 92 | |||||
fMAX | Maximum switching frequency | DDC channels enabled | 400 | kHz |
PARAMETER | PINS | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
tPLH | Propagation delay | A to B | CEC channels enabled | 450 | ns | ||
B to A | 160 | ||||||
tPLH | A to B | 13 | µs | ||||
B to A | 0.251 | ||||||
tf | A port fall time | A Port | CEC channels enabled | 71 | ns | ||
B port fall time | B Port | 96 | |||||
tr | A port rise time | A Port | CEC channels enabled | 194 | ns | ||
B port rise time | B Port | 15 | µs |
PARAMETER | PINS | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
tPLH | Propagation delay | B to A | CEC channels enabled | 10 | µs | ||
tPLH | B to A | 9 | |||||
tf | A port fall time | A Port | CEC channels enabled | 0.35 | ns | ||
tr | A port rise time | A Port | CEC channels enabled | 0.37 | ns |
PIN | CL |
---|---|
DDC, CEC (A side) | 750 pF |
DDC, CEC, HPD (B side) |
15 pF |
The TPD12S015 is an integrated interface solution for HDMI 1.3 and 1.4 interfaces, for both portable and non-portable electronics applications. The device has a boost DC-DC converter that uses the 2.3-V to 5.5-V internal power supply and outputs regulated 5-V standard compliant power supply to the cable. This power supply output has current limit and short-circuit protection function. There are bidirectional level-shifting and signal-conditioning circuits on CEC, SCL, and SDA with pullup resistors integrated to minimize the external passive discrete component use. There is also a unidirectional level shifter for HPD signal that translates the 5-V HPD down to VCCA level. The HPD_B port has a glitch filter to avoid false detection due to the bouncing while inserting the HDMI plug. For the eight TMDS lines, there are high-speed ESD diodes on each line to make sure that the system pass 8-kV contact ESD.
The HDMI cable side of the DDC lines incorporates rise-time accelerators to support the high-capacitive load on the HDMI cable side. The rise-time accelerator boosts the cable side DDC signal, independent to which side of the bus is releasing the signal.
The TPD12S015 has incorporated all the required pullup and pulldown resistors at the interface pins. The system is designed to work properly with no external pullup resistors on the DDC, CEC, and HPD lines. For proper system operation, no external resistors are placed at the A and B ports. If there are internal pullups at the host processor, they must be disabled.
The undervoltage lockout circuit prevents the DC-DC converter from malfunctioning at low input voltages and from excessive discharge of the battery. It disables the output stage of the converter once the falling VIN trips the undervoltage lockout threshold VBATUV. The undervoltage lockout threshold VBATUV for falling VIN is typically 2 V. The device starts operation once the rising VIN trips undervoltage lockout threshold VBATUV again at typical 2.1 V.
The DC-DC converter has an internal soft-start circuit that controls the ramp-up of the output voltage. The output voltage reaches its nominal value within tStart of typically 250 µs after CT_CP_HPD pin has been pulled to high level. The output voltage ramps up from 5% to its nominal value within tRamp of 300 µs. This limits the inrush current in the converter during start-up and prevents possible input voltage drops when a battery or high-impedance power source is used. During soft start, the switch current limit is reduced to 300 mA until the output voltage reaches VIN. Once the output voltage trips this threshold, the device operates with its nominal current limit ILIMF.
The TPD12S015 enables DDC translation from VCCA (system side) voltage levels to 5-V (HDMI cable side) voltage levels without degradation of system performance. The TPD12S015 contains two bidirectional open-drain buffers specifically designed to support up-translation or down-translation between the low voltage, VCCA side DDC-bus, and the 5-V DDC-bus. The port B I/Os are overvoltage tolerant to 5.5 V even when the device is unpowered. After power up and with the LS_OE and CT_CP_HPD pins high, a low level on port A (below approximately VILC = 0.08 × VCCA V) turns the corresponding port B driver (either SDA or SCL) on and drives port B down to VOLB V. When port A rises above approximately 0.10 × VCCA V, the port B pulldown driver is turned off and the internal pullup resistor pulls the pin high. When port B falls first and goes below 0.3 × 5VOUT, a CMOS hysteresis input buffer detects the falling edge, turns on the port A driver, and pulls port A down to approximately VOLA = 0.16 × VCCA V. The port B pulldown is not enabled unless the port A voltage goes below VILC. If the port A low voltage goes below VILC, the port B pulldown driver is enabled until port A rises above (VILC + ΔVT-HYSTA), then port B, if not externally driven LOW, continues to rise being pulled up by the internal pullup resistor.
The CEC level-shifting function operates in the same manner as the DDC lines except that the CEC line does not need the rise time accelerator function.
The DC-DC converter is enabled when the CT_CP_HPD is set to high. At first, the internal reference is activated and the internal analog circuits are settled. Afterwards, the soft start is activated and the output voltage is ramped up. The output voltage reaches its nominal value in typically 250 µs after the device has been enabled. The CT_CP_HPD input can be used to control power sequencing in a system with various DC-DC converters. The CT_CP_HPD pin can be connected to the output of another converter, to drive the EN pin high and getting a sequencing of supply rails. With CT_CP_HPD = GND, the DC-DC enters shutdown mode.
The TPD12S015 integrates a power save mode to improve efficiency at light load. In power save mode, the converter only operates when the output voltage trips below a set threshold voltage. It ramps up the output voltage with several pulses and goes into power save mode once the output voltage exceeds the set threshold voltage. The PFM mode is left and PWM mode entered in case the output current can not longer be supported in PFM mode.