The TPD12S520 is a single-chip electro-static discharge (ESD) circuit protection device for the high-definition multimedia interface (HDMI) receiver port. While providing ESD protection with transient voltage suppression (TVS) diodes, the TVS protection adds little or no additional glitch in the high-speed differential signals. The high-speed transition minimized differential signaling (TMDS) ESD protection lines add only 0.8-pF capacitance.
The low-speed control lines offer voltage-level shifting to eliminate the need for an external voltage level-shifter IC. The control line TVS diodes add 3.5-pF capacitance to the control lines. The 38-pin DBT package offers a seamless layout routing option to eliminate the routing glitch for the differential signal pairs. The DBT package pitch (0.5 mm) matches with the HDMI connector pitch. In addition, the pin mapping follows the same order as the HDMI connector pin mapping. This HDMI receiver port protection and interface device is designed specifically for HDMI receiver-interface protection. The 24-pin RMN package offers flow through routing using only two layers for highly integrated, space-efficient full HDMI protection.
DEVICE NAME | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPD12S520 | TSSOP (38) | 6.40 mm × 9.70 mm |
WQFN (24) | 4.50 mm × 1.50 mm |
Changes from E Revision (September 2014) to F Revision
Changes from D Revision (December 2013) to E Revision
Changes from C Revision (April 2009) to D Revision
NAME | PIN NO. | TYPE | ESD LEVEL | DESCRIPTION | |
---|---|---|---|---|---|
DBT | RMN | ||||
5V_SUPPLY | 1 | 12 | PWR | 2 kV(4) | Bias for TMDS protection |
LV_SUPPLY | 2 | 13 | PWR | 2 kV(4) | Bias for CE/DDC/HOTPLUG level shifters |
GND, TMDS_GND | 3, 5, 8, 11,14, 25, 28, 31, 34, 36 |
6, 9, 10, 14, 17 | GND | NA | TMDS ESD and parasitic GND return(5) |
TMDS_D2+ | 4, 35 | 18 | IO | 8 kV(3) | TMDS 0.8-pF ESD protection(1) |
TMDS_D2– | 6, 33 | 19 | IO | 8 kV(3) | TMDS 0.8-pF ESD protection(1) |
TMDS_D1+ | 7, 32 | 15 | IO | 8 kV(3) | TMDS 0.8-pF ESD protection(1) |
TMDS_D1– | 9, 30 | 16 | IO | 8 kV(3) | TMDS 0.8-pF ESD protection(1) |
TMDS_D0+ | 10, 29 | 8 | IO | 8 kV(3) | TMDS 0.8-pF ESD protection(1) |
TMDS_D0– | 12, 27 | 7 | IO | 8 kV(3) | TMDS 0.8-pF ESD protection(1) |
TMDS_CK+ | 13, 26 | 5 | IO | 8 kV(3) | TMDS 0.8-pF ESD protection(1) |
TMDS_CK– | 15, 24 | 4 | IO | 8 kV(3) | TMDS 0.8-pF ESD protection(1) |
CE_REMOTE_IN | 16 | 20 | IO | 2 kV(4) | LV_SUPPLY referenced logic level into ASIC |
DDC_CLK_IN | 17 | 21 | IO | 2 kV(4) | LV_SUPPLY referenced logic level into ASIC |
DDC_DAT_IN | 18 | 22 | IO | 2 kV(4) | LV_SUPPLY referenced logic level into ASIC |
HOTPLUG_DET_IN | 19 | 23 | IO | 2 kV(4) | LV_SUPPLY referenced logic level into ASIC |
HOTPLUG_DET_OUT | 20 | 24 | IO | 8 kV(3) | 5 V_SUPPLY referenced logic level out, plus 3.5-pF ESD(2) to connector |
DDC_DAT_OUT | 21 | 1 | IO | 8 kV(3) | 5 V_SUPPLY referenced logic level out, plus 3.5-pF ESD to connector |
DDC_CLK_OUT | 22 | 2 | IO | 8 kV(3) | 5 V_SUPPLY referenced logic level out, plus 3.5-pF ESD to connector |
CE_REMOTE_OUT | 23 | 3 | IO | 8 kV(3) | 5 V_SUPPLY referenced logic level out, plus 3.5-pF ESD to connector |
ESD_BYP | 37 | 11 | IO | 2 kV(4) | ESD bypass. This pin must be connected to a 0.1-μF ceramic capacitor. |
NC | 38 | NA | No connection |