TPD12S520 Single-Chip HDMI Receiver Port Protection and Interface Device
- SLVS640F October 2007 – February 2015 TPD12S520
  
  PRODUCTION DATA.

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DATA SHEET

TPD12S520 Single-Chip HDMI Receiver Port Protection and Interface Device

1 Features

IEC 61000-4-2 Level 4 ESD Protection
- ±8-kV Contact Discharge on External Lines
Single-Chip ESD Solution for HDMI Driver
12 Channel ESD Protection Diodes
Supports All HDMI 1.3 and HDMI 1.4b Data Rates
(–3 dB Frequency > 3 GHz)
0.8-pF Capacitance for the High Speed TMDS Lines
0.05-pF Matching Capacitance Between the Differential Signal Pair
38-Pin TSSOP Provides Seamless Layout Option with HDMI Connector
24-Pin WQFN Package for Space Constrained Applications
Backdrive Protection
Lead-Free Package

2 Applications

Video Interface
Consumer Electronics
Displays and Digital Televisions
Handheld Displays

3 Description

The TPD12S520 is a single-chip electro-static discharge (ESD) circuit protection device for the high-definition multimedia interface (HDMI) receiver port. While providing ESD protection with transient voltage suppression (TVS) diodes, the TVS protection adds little or no additional glitch in the high-speed differential signals. The high-speed transition minimized differential signaling (TMDS) ESD protection lines add only 0.8-pF capacitance.

The low-speed control lines offer voltage-level shifting to eliminate the need for an external voltage level-shifter IC. The control line TVS diodes add 3.5-pF capacitance to the control lines. The 38-pin DBT package offers a seamless layout routing option to eliminate the routing glitch for the differential signal pairs. The DBT package pitch (0.5 mm) matches with the HDMI connector pitch. In addition, the pin mapping follows the same order as the HDMI connector pin mapping. This HDMI receiver port protection and interface device is designed specifically for HDMI receiver-interface protection. The 24-pin RMN package offers flow through routing using only two layers for highly integrated, space-efficient full HDMI protection.

Device Information⁽¹⁾

DEVICE NAME	PACKAGE	BODY SIZE (NOM)
TPD12S520	TSSOP (38)	6.40 mm × 9.70 mm
TPD12S520	WQFN (24)	4.50 mm × 1.50 mm

For all available packages, see the orderable addendum at the end of the datasheet.

Circuit Protection Scheme

4 Revision History

Changes from E Revision (September 2014) to F Revision

Added clarification to HDMI data rates.Go
Added clarification to HDMI data rates.Go

Changes from D Revision (December 2013) to E Revision

Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go

Changes from C Revision (April 2009) to D Revision

Added new application to Applications section. Go
Added RMN Package to Datasheet. Go
Updated RMN Package. Go
Updated Pin Description Table. Go
Added additonal graphs to Typical Performance section. Go

5 Pin Configuration and Functions

Pin Functions

NAME	PIN NO.		TYPE	ESD LEVEL	DESCRIPTION
NAME	DBT	RMN	TYPE	ESD LEVEL	DESCRIPTION
5V_SUPPLY	1	12	PWR	2 kV⁽⁴⁾	Bias for TMDS protection
LV_SUPPLY	2	13	PWR	2 kV⁽⁴⁾	Bias for CE/DDC/HOTPLUG level shifters
GND, TMDS_GND	3, 5, 8, 11,14, 25, 28, 31, 34, 36	6, 9, 10, 14, 17	GND	NA	TMDS ESD and parasitic GND return⁽⁵⁾
TMDS_D2+	4, 35	18	IO	8 kV^⁽³⁾	TMDS 0.8-pF ESD protection⁽¹⁾
TMDS_D2–	6, 33	19	IO	8 kV⁽³⁾	TMDS 0.8-pF ESD protection⁽¹⁾
TMDS_D1+	7, 32	15	IO	8 kV⁽³⁾	TMDS 0.8-pF ESD protection⁽¹⁾
TMDS_D1–	9, 30	16	IO	8 kV⁽³⁾	TMDS 0.8-pF ESD protection⁽¹⁾
TMDS_D0+	10, 29	8	IO	8 kV⁽³⁾	TMDS 0.8-pF ESD protection⁽¹⁾
TMDS_D0–	12, 27	7	IO	8 kV⁽³⁾	TMDS 0.8-pF ESD protection⁽¹⁾
TMDS_CK+	13, 26	5	IO	8 kV⁽³⁾	TMDS 0.8-pF ESD protection⁽¹⁾
TMDS_CK–	15, 24	4	IO	8 kV⁽³⁾	TMDS 0.8-pF ESD protection⁽¹⁾
CE_REMOTE_IN	16	20	IO	2 kV⁽⁴⁾	LV_SUPPLY referenced logic level into ASIC
DDC_CLK_IN	17	21	IO	2 kV⁽⁴⁾	LV_SUPPLY referenced logic level into ASIC
DDC_DAT_IN	18	22	IO	2 kV⁽⁴⁾	LV_SUPPLY referenced logic level into ASIC
HOTPLUG_DET_IN	19	23	IO	2 kV⁽⁴⁾	LV_SUPPLY referenced logic level into ASIC
HOTPLUG_DET_OUT	20	24	IO	8 kV⁽³⁾	5 V_SUPPLY referenced logic level out, plus 3.5-pF ESD⁽²⁾ to connector
DDC_DAT_OUT	21	1	IO	8 kV⁽³⁾	5 V_SUPPLY referenced logic level out, plus 3.5-pF ESD to connector
DDC_CLK_OUT	22	2	IO	8 kV⁽³⁾	5 V_SUPPLY referenced logic level out, plus 3.5-pF ESD to connector
CE_REMOTE_OUT	23	3	IO	8 kV⁽³⁾	5 V_SUPPLY referenced logic level out, plus 3.5-pF ESD to connector
ESD_BYP	37	11	IO	2 kV⁽⁴⁾	ESD bypass. This pin must be connected to a 0.1-μF ceramic capacitor.
NC	38			NA	No connection

(1) These two pins must be connected together inline on the PCB.

(2) This output can be connected to an external 0.1-μF ceramic capacitor, resulting in an increased ESD withstand voltage rating.

(3) Standard IEC 61000-4-2, C_DISCHARGE = 150 pF, R_DISCHARGE = 330 Ω, 5V_SUPPLY and LV_SUPPLY within recommended operating conditions, GND = 0 V, and ESD_BYP (pin 37) and HOTPLUG_DET_OUT (pin 20) each bypassed with a 0.1-μF ceramic capacitor connected to GND.

(4) Human body model (HBM) per MIL-STD-883, Method 3015, C_DISCHARGE = 100 pF, R_DISCHARGE = 1.5 kΩ, 5V_SUPPLY and LV_SUPPLY within recommended operating conditions, GND = 0 V, and ESD_BYP (pin 37) and HOTPLUG_DET_OUT (pin 20) each bypassed with a 0.1-μF ceramic capacitor connected to GND.

(5) These pins should be routed directly to the associated GND pins on the HDMI connector, with single-point ground vias at the connector.

6 Specifications

6.1 Absolute Maximum Ratings⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
V_{5V_SUPPLY}	Supply voltage	–0.3	6	V
V_{LV_SUPPLY}	Supply voltage	–0.3	6	V
V_I/O	DC voltage at any channel input	–0.5	6	V
T_A	Operating Free Air Temperature	–40	85	°C
T_stg	Storage temperature range	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

				VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per MIL-STD-883, Method 3015, C_DISCHARGE = 100 pF, R_DISCHARGE = 1.5 kΩ⁽¹⁾	See Pin Configuration and Functions	±2000	V
V_(ESD)	Electrostatic discharge	IEC 61000-4-2 Contact Discharge⁽²⁾	See Pin Configuration and Functions	±8000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	TYP	MAX	UNIT
T_A	Operating free-air temperature	–40		85	°C
5V_SUPPLY	Operating supply voltage	GND	5	5.5	V
LV_SUPPLY	Bias supply voltage	1	3.3	5.5	V

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPD12S520		UNIT
		DBT	RMN
		38 PINS	24 PINS
R_θJA	Junction-to-ambient thermal resistance	83.6	80.8	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	29.8	36.4
R_θJB	Junction-to-board thermal resistance	44.7	27.1
ψ_JT	Junction-to-top characterization parameter	2.9	1.4
ψ_JB	Junction-to-board characterization parameter	44.1	27.0

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS			MIN	TYP	MAX	UNIT
I_5V	Operating supply current	5V_SUPPLY = 5 V				1	5	µA
I_LV	Bias supply current	LV_SUPPLY = 3.3 V				1	2	mA
I_OFF	OFF-state leakage current, level-shifting NFET	LV_SUPPLY = 0 V				0.1	1	µA
I_{BACK DRIVE}	Current conducted from output pins to V_SUPPLY rails when powered down	5V_SUPPLY < V_{CH_OUT}	TMDS_D[2:0]+/–, TMDS_CK+/–, CE_REMOTE_OUT, DDC_DAT_OUT, DDC_CLK_OUT, HOTPLUG_DET_OUT			0.1	5	µA
V_ON	Voltage drop across level-shifting NFET when ON	LV_SUPPLY = 2.5 V, V_S = GND, I_DS = 3 mA			75	95	140	mV
V_F	Diode forward voltage	I_F = 8 mA,	Top diode			1		V
V_F	Diode forward voltage	T_A = 25°C⁽¹⁾	Bottom diode			1		V
V_CL	Channel clamp voltage at ±8 kV HBM ESD	TA = 25°C⁽¹⁾⁽²⁾	Positive transients			9		V
V_CL	Channel clamp voltage at ±8 kV HBM ESD	TA = 25°C⁽¹⁾⁽²⁾	Negative transients			-9		V
R_DYN	Dynamic resistance	I = 1 A, T_A = 25°C⁽³⁾	Positive transients			0.6		Ω
R_DYN	Dynamic resistance	I = 1 A, T_A = 25°C⁽³⁾	Negative transients			0.5		Ω
I_LEAK	TMDS channel leakage current	T_A = 25°C⁽¹⁾				0.01	1	µA
C_IN, TMDS	TMDS channel input capacitance	5V_SUPPLY= 5 V, Measured at 1 MHz, V_BIAS= 2.5 V⁽¹⁾				0.8	1.0	pF
ΔC_IN, TMDS	TMDS channel input capacitance matching	5V_SUPPLY= 5 V, Measured at 1 MHz, V_BIAS= 2.5 V⁽¹⁾⁽⁴⁾				0.05		pF
C_MUTUAL	Mutual capacitance between signal pin and adjacent signal pin	5V_SUPPLY= 0 V, Measured at 1 MHz, V_BIAS= 2.5 V⁽¹⁾				0.07		pF
C_IN	Level-shifting input capacitance, capacitance to GND	5V_SUPPLY= 0 V, Measured at 100 KHz, V_BIAS= 2.5 V⁽¹⁾		DDC		3.5	4	pF
				CEC		3.5	4
				HP		3.5	4

(1) This parameter is specified by design and verified by device characterization

(2) Human-Body Model (HBM) per MIL-STD-883, Method 3015, C_DISCHARGE = 100 pF, R_DISCHARGE = 1.5 kΩ

(3) These measurements performed with no external capacitor on ESD_BYP.

(4) Intrapair matching, each TMDS pair (i.e., D+, D–)

6.6 Typical Characteristics

Figure 1. TPD12S520RMN IEC Clamping Waveforms +8kV Contact

Figure 3. I_LEAK vs. Temperature VIN = 5.0V

Figure 5. Insertion Loss Performance Across Frequency

Figure 2. TPD12S520RMN IEC Clamping Waveforms -8kV Contact

Figure 4. Capacitance vs. V_BIAS