SLVS639F October   2007  – February 2016 TPD12S521

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Circuit Protection Scheme
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Single-Chip ESD Solution for HDMI Driver
      2. 8.3.2 Supports All HDMI 1.3 and HDMI 1.4b Data Rates
      3. 8.3.3 Integrated Level Shifting for the Control Lines
      4. 8.3.4 ±8-kV Contact ESD Protection on External Lines
      5. 8.3.5 38-Pin TSSOP Provides Seamless Layout Option With HDMI Connector
      6. 8.3.6 Backdrive Protection
      7. 8.3.7 Lead-Free Package
      8. 8.3.8 On-Chip Current Regulator With 55-mA Current Output
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DBT|38
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

TPD12S521 po_lvs639.eps

Pin Functions

PIN TYPE ESD DESCRIPTION
NAME NO.
5V_SUPPLY 1 PWR 2 kV(1) Current source for 5V_OUT.
LV_SUPPLY 2 Bias for CE/DDC/HOTPLUG level shifters.
GND, TMDS_GND 3, 5, 8, 11,14, 25, 28, 31, 34, 36 GND NA TMDS ESD and parasitic GND return.
TMDS_D2+ 4, 35 ESD clamp 8 kV(2) TMDS 0.8-pF ESD protection.(3)
TMDS_D2– 6, 33
TMDS_D1+ 7, 32
TMDS_D1– 9, 30
TMDS_D0+ 10, 29
TMDS_D0– 12, 27
TMDS_CK+ 13, 26
TMDS_CK– 15, 24
CE_REMOTE_IN 16 IO 2 kV(1) LV_SUPPLY referenced logic level into ASIC.
DDC_CLK_IN 17
DDC_DAT_IN 18
HOTPLUG_DET_IN 19
HOTPLUG_DET_OUT 20 IO, ESD clamp 8 kV(2) 5 V_SUPPLY referenced logic level out, plus 3.5-pF ESD(4) to connector.
DDC_DAT_OUT 21 5 V_SUPPLY referenced logic level out, plus 3.5-pF ESD to connector.
DDC_CLK_OUT 22
CE_REMOTE_OUT 23 IO, ESD clamp 8 kV(2) 3.3-V_SUPPLY referenced logic level out, plus 3.5-pF ESD to connector.
ESD_BYP 37 ESD Bypass 2 kV(1) ESD bypass. This pin must be connected to a 0.1-µF ceramic capacitor.
5V_OUT 38 PWR 2 kV(1) 5-V regulator output
(1) Human-Body Model (HBM) per MIL-STD-833, Method 3015, CDISCHARGE = 100 pF, RDISCHARGE = 1.5 kΩ, 5V_SUPPLY and LV_SUPPLY within recommended operating conitions, GND = 0 V, and ESD_BYP (pin 37) and HOTPLUG_DET_OUT (pin 20) each bypassed with a 0.1-µF ceramic capacitor connnected to GND.
(2) Standard IEC 61000-4-2, CDISCHARGE = 150 pF, RDISCHARGE = 330 Ω, 5V_SUPPLY and LV_SUPPLY within recommended operating conditions, GND = 0 V, and ESD_BYP (pin 37) and HOTPLUG_DET_OUT (pin 20) each bypassed with a 0.1-µF ceramic capacitor connected to GND.
(3) These two pins must be connected together inline on the PCB.
(4) This output can be connected to an external 0.1-µF ceramic capacitor, resulting in an increased ESD withstand voltage rating.