SLVSDN7B
August 2016 – February 2022
TPD1E10B06-Q1
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
ESD Ratings - AEC Specification
6.2
ESD Ratings—IEC Specification
6.3
ESD Ratings—ISO Specification
6.4
Recommended Operating Conditions
6.5
Thermal Information
6.6
Electrical Characteristics
6.7
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
AEC-Q101 Qualified
7.3.2
IEC 61000-4-2 ESD Protection
7.3.3
ISO 10605 ESD Protection
7.3.4
IEC 61000-4-5 Surge Protection
7.3.5
IO Capacitance
7.3.6
Dynamic Resistance
7.3.7
DC Breakdown Voltage
7.3.8
Ultra Low Leakage Current
7.3.9
Clamping Voltage
7.3.10
Industrial Temperature Range
7.3.11
Space-Saving Footprint
7.4
Device Functional Modes
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.3
Application Curves
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
11
Device and Documentation Support
11.1
Documentation Support
11.1.1
Related Documentation
11.2
Receiving Notification of Documentation Updates
11.3
Support Resources
11.4
Trademarks
11.5
Electrostatic Discharge Caution
11.6
Glossary
12
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
DPY|2
MPSS034D
DYA|2
MPSS124A
Thermal pad, mechanical data (Package|Pins)
Orderable Information
slvsdn7b_oa
slvsdn7b_pm
7
Detailed Description