SLVSDN8B august   2016  – september 2023 TPD1E10B09-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings—AEC Specification
    3. 6.3 ESD Ratings—IEC Specification
    4. 6.4 ESD Ratings—ISO Specification
    5. 6.5 Recommended Operating Conditions
    6. 6.6 Thermal Information
    7. 6.7 Electrical Characteristics
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  AEC-Q101 Qualified
      2. 7.3.2  IEC 61000-4-2 ESD Protection
      3. 7.3.3  ISO 10605 ESD Protection
      4. 7.3.4  IEC 61000-4-5 Surge Protection
      5. 7.3.5  IO Capacitance
      6. 7.3.6  Dynamic Resistance
      7. 7.3.7  DC Breakdown Voltage
      8. 7.3.8  Ultra Low Leakage Current
      9. 7.3.9  Clamping Voltage
      10. 7.3.10 Industrial Temperature Range
      11. 7.3.11 Space-Saving Footprint
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.2 Detailed Design Procedure

To begin the design process, some parameters must be decided upon; the designer must make sure:

  • The voltage range on the protected line does not exceed the reverse standoff voltage of the TVS diode(s) (VRWM).
  • The operating frequency is supported by the I/O capacitance, CIO, of the TVS diode.
  • The IEC 61000-4-2 protection requirement is covered by the IEC performance of the TVS diode.

For this application, the audio signal voltage range is –8 V to 8 V. The VRWM for the TVS is –9.5 V to 9.5 V; therefore, the bidirectional TVS does not break down during normal operation, and normal operation of the audio signal is not affected due to the signal voltage range. In this application, a bidirectional TVS like the TPD1E10B09-Q1 is required.

Next, consider the frequency content of this audio signal. In this application with the class AB amplifier, the frequency content is from 20 Hz to 20 kHz; ensure that the TVS I/O capacitance does not distort this signal by filtering it. With the TPD1E10B09-Q1 typical capacitance of 10 pF, which leads to a typical cutoff frequency of just under 500 MHz, this diode has sufficient bandwidth to pass the audio signal without distorting it.

Finally, the human interface in this application requires protection for ±15-kV Contact and ±15-kV Air-Gap ESD, which is above the standard Level 4 IEC 61000-4-2 system-level ESD protection. A standard TVS cannot survive this level of IEC ESD stress. However, the TPD1E10B09-Q1 can survive at least ±20-kV Contact and ±20-kV Air-Gap ESD. Therefore, the device can provide sufficient ESD protection for the interface, even though the requirements are stringent. For any TVS diode to provide its full range of ESD protection capabilities, as well as to minimize the noise and EMI disturbances the board will see during ESD events, it is crucial that a system designer uses proper board layout of their TVS ESD protection diodes. See the Layout section for instructions on properly laying out the TPD1E10B09-Q1.