SLVSDN8B
august 2016 – september 2023
TPD1E10B09-Q1
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings—AEC Specification
6.3
ESD Ratings—IEC Specification
6.4
ESD Ratings—ISO Specification
6.5
Recommended Operating Conditions
6.6
Thermal Information
6.7
Electrical Characteristics
6.8
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
AEC-Q101 Qualified
7.3.2
IEC 61000-4-2 ESD Protection
7.3.3
ISO 10605 ESD Protection
7.3.4
IEC 61000-4-5 Surge Protection
7.3.5
IO Capacitance
7.3.6
Dynamic Resistance
7.3.7
DC Breakdown Voltage
7.3.8
Ultra Low Leakage Current
7.3.9
Clamping Voltage
7.3.10
Industrial Temperature Range
7.3.11
Space-Saving Footprint
7.4
Device Functional Modes
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.3
Application Curves
8.3
Power Supply Recommendations
8.4
Layout
8.4.1
Layout Guidelines
8.4.2
Layout Example
9
Device and Documentation Support
9.1
Documentation Support
9.1.1
Related Documentation
9.2
Receiving Notification of Documentation Updates
9.3
Support Resources
9.4
Trademarks
9.5
Electrostatic Discharge Caution
9.6
Glossary
10
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
DPY|2
MPSS034D
Thermal pad, mechanical data (Package|Pins)
Orderable Information
slvsdn8b_oa
slvsdn8b_pm
6.2
ESD Ratings—AEC Specification
VALUE
UNIT
V
(ESD)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002
(1)
±2500
V
Charged-device model (CDM), per AEC Q100-011
±1000
(1)
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.