SLVSDN8B august   2016  – september 2023 TPD1E10B09-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings—AEC Specification
    3. 6.3 ESD Ratings—IEC Specification
    4. 6.4 ESD Ratings—ISO Specification
    5. 6.5 Recommended Operating Conditions
    6. 6.6 Thermal Information
    7. 6.7 Electrical Characteristics
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  AEC-Q101 Qualified
      2. 7.3.2  IEC 61000-4-2 ESD Protection
      3. 7.3.3  ISO 10605 ESD Protection
      4. 7.3.4  IEC 61000-4-5 Surge Protection
      5. 7.3.5  IO Capacitance
      6. 7.3.6  Dynamic Resistance
      7. 7.3.7  DC Breakdown Voltage
      8. 7.3.8  Ultra Low Leakage Current
      9. 7.3.9  Clamping Voltage
      10. 7.3.10 Industrial Temperature Range
      11. 7.3.11 Space-Saving Footprint
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.7 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITION MIN TYP MAX UNIT
VRWM Reverse stand-off voltage Pin 1 to 2 or pin 2 to 1 9 V
ILEAK Leakage current Pin 1 = 5 V, pin 2 = 0 V 100 nA
VClamp1,2 Clamp voltage with ESD strike on pin 1, pin 2 grounded IPP = 1 A, tp = 8/20 μs(2) 13 V
IPP = 5 A, tp = 8/20 μs(2) 17
VClamp2,1 Clamp voltage with ESD strike on pin 2, pin 1 grounded IPP = 1 A, tp = 8/20 μs(2) 13 V
IPP = 4.5 A, tp = 8/20 μs(2) 20
RDYN Dynamic resistance Pin 1 to pin 2(1) 0.5 Ω
Pin 2 to pin 1(1) 0.5
CIO I/O capacitance VIO = 2.5 V; f = 1 MHz 10 pF
VBR1,2 Break-down voltage, pin 1 to pin 2 IIO = 1 mA 9.5 V
VBR2,1 Break-down voltage, pin 2 to pin 1 IIO = 1 mA 9.5 V
(1) Extraction of RDYN using least squares fit of TLP characteristics from IPP = 10 A to IPP = 20 A.
(2) Non-repetitive current pulse 8/20 µs exponentially decaying waveform according to IEC 61000-4-5.