SLLSEH9B October 2013 – July 2016 TPD1S414
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
TPD1S414 can be routed in a single-layer PCB. PCB traces to VBUS_SYS, VBUS_CON, and GND can be routed in the fashion shown in Figure 12.
Shorting all of the VBUS_SYS pins together, all the VBUS_CON pins together, and all the GND pins together helps provide the lowest resistance between the USB connector and the PMIC. For this example, the trace widths to VBUS_SYS, VBUS_CON are 25 mils (0.635 mm) under TPD1S414. There are no VIAs required within the SMD pads in this design. Stitching VIAs for GND can be placed near the component instead.
The decoupling capacitors per the Recommended Operating Conditions must be placed as close as possible to the TPD1S414. There must be a short path from the device ground pins to the system ground plane. This ensures best protection under ESD and surge transients.