SLLS684I July   2006  – March 2016 TPD2E001

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 ESD Ratings: Surge Protection
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Signal Range on IO1 and IO2 and VCC Pins
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Power pin voltage –0.3 7 V
VIO IO pin voltage –0.3 VCC + 0.3 V
TJ Junction temperature 150 °C
Bump temperature (soldering) Infrared (15 s) 220 °C
Vapor phase (60 s) 215
Lead temperature (soldering, 10 s) 300 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute-maximum-rating conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±15000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 ESD Ratings: Surge Protection

VALUE UNIT
V(ESD) Electrostatic discharge IEC 61000-4-2 contact ±8000 V
IEC 61000-4-2 air-gap discharge ±15000

6.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
TA, operating free-air temperature –40 85 °C
Operating voltage VCC pin 0.9 5.5 V
IO1, IO2 pins 0 VCC

6.5 Thermal Information

THERMAL METRIC(1) TPD2E001 UNIT
DRY (USON) DRL (SOT) DRS (WSON) DZD (SOP)
5 PINS 5 PINS 6 PINS 4 PINS
RθJA Junction-to-ambient thermal resistance 374.2 257.6 91.9 213.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 223.4 97.6 106.9 93.5 °C/W
RθJB Junction-to-board thermal resistance 227.8 74.2 64.8 56.8 °C/W
ψJT Junction-to-top characterization parameter 52.9 7.5 10.2 4.2 °C/W
ψJB Junction-to-board characterization parameter 224.8 73.7 64.9 56.4 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 87.5 N/A 29.9 N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.6 Electrical Characteristics

VCC = 5 V ± 10%, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
VCC Supply voltage 0.9 5.5 V
ICC Supply current 1 100 nA
VF Diode forward voltage IF = 10 mA 0.65 0.95 V
VBR Breakdown voltage IBR = 10 mA 11 V
VC Channel clamp voltage(2) TA = 25°C, ±15-kV HBM,
IF = 10 A		 Positive transients VCC + 25 V
Negative transients –25
TA = 25°C,
±8-kV contact discharge
(IEC 61000-4-2), IF = 24 A		 Positive transients VCC + 60
Negative transients –60
TA = 25°C,
±15-kV air-gap discharge
(IEC 61000-4-2), IF = 45 A		 Positive transients VCC + 100
Negative transients –100
IIO Channel leakage current VI/O = GND to VCC –1 1 nA
CIO Channel input capacitance VCC = 5 V, bias of VCC / 2; ƒ = 10 MHz 1.5 pF
(1) Typical values are at VCC = 5 V and TA = 25 °C
(2) Channel clamp voltage is not production tested.

6.7 Typical Characteristics

TPD2E001 iocap_iovolt_lls682.gif
Figure 1. IO Capacitance vs IO Voltage (VCC = 5 V)
TPD2E001 C003_SLLS684.png Figure 3. TLP IO to GND (DRS Package)
TPD2E001 leak_ta_lls682.gif
Figure 2. IO Leakage Current vs Temperature (VCC = 5 V)
TPD2E001 C004_SLLS684.png Figure 4. TLP GND to IO (DRS Package)