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  • TPD2S300 USB Type C Short-to-VBUS and IEC ESD Protector for the CC Pins

    • SLVSDL1 April   2017 TPD2S300

      PRODUCTION DATA.  

  • CONTENTS
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  • TPD2S300 USB Type C Short-to-VBUS and IEC ESD Protector for the CC Pins
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings—JEDEC Specification
    3. 6.3 ESD Ratings—IEC Specification
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 2-Channels of Short-to-VBUS Overvoltage Protection (CC1, CC2 Pins): 24-VDC Tolerant
      2. 7.3.2 2-Channels of IEC61000-4-2 ESD Protection (CC1, CC2 Pins)
      3. 7.3.3 Low Quiescent Current: 3.23 µA (Typical), VPWR, VM = 3.3 V
      4. 7.3.4 CC1, CC2 Overvoltage Protection FETs 200 mA Capable for Passing VCONN Power
      5. 7.3.5 CC Dead Battery Resistors Integrated for Handling Dead Battery Use Case in Mobile Devices
      6. 7.3.6 1.4-mm × 1.4-mm WCSP Package
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Smart-Phone Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 VBIAS Capacitor Selection
          2. 8.2.1.2.2 Dead Battery Operation
          3. 8.2.1.2.3 CC Line Capacitance
          4. 8.2.1.2.4 FLT Pin Operation
          5. 8.2.1.2.5 VCONN Operation
          6. 8.2.1.2.6 Low Quiescent Current
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Laptop Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 VBIAS Capacitor Selection
          2. 8.2.2.2.2 Dead Battery Operation
          3. 8.2.2.2.3 CC Line Capacitance
          4. 8.2.2.2.4 FLT Pin Operation
          5. 8.2.2.2.5 VCONN Operation
        3. 8.2.2.3 Application Curves
      3. 8.2.3 Power Adaptor Application
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
          1. 8.2.3.2.1 VBIAS Capacitor Selection
          2. 8.2.3.2.2 Dead Battery Operation
          3. 8.2.3.2.3 CC Line Capacitance
          4. 8.2.3.2.4 FLT Pin Operation
          5. 8.2.3.2.5 VCONN Operation
        3. 8.2.3.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
  13. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
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    • MXBG144B
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DATA SHEET

TPD2S300 USB Type C Short-to-VBUS and IEC ESD Protector for the CC Pins

1 Features

  • 2 Channels of Short-to-VBUS Overvoltage Protection (CC1, CC2): 24-VDC Tolerant
  • 2 Channels of IEC 61000-4-2 ESD Protection (CC1, CC2)
  • Low quiescent current: 3.23 µA (Typical), VPWR, VM = 3.3 V
  • CC1, CC2 Overvoltage Protection FETs 200 mA capable for passing VCONN power
  • CC Dead Battery Resistors Integrated for handling dead battery use case in mobile devices
  • 1.4-mm × 1.4-mm WCSP Package

2 Applications

  • Smartphones
  • Laptop PC
  • Tablets
  • Wall Adaptors
  • Power Banks
  • Power Drills

3 Description

The TPD2S300 is a single chip USB Type-C port protection solution that provides 20-V Short-to-VBUS overvoltage and IEC ESD protection for the CC1 and CC2 pins.

Since the release of the USB Type-C connector, many products and accessories for USB Type-C have been released which do not meet the USB Type-C specification. One example of this is USB Type-C Power Delivery adaptors that start out with 20 V on the VBUS line. Another concern for USB Type-C is that mechanical twisting and sliding of the connector could short pins due to the close proximity they have in this small connector. This can cause 20-V VBUS to be shorted to the CC pins. Also, due to the close proximity of the pins in the Type-C connector, there is a heightened concern that debris and moisture is going to cause the 20-V VBUS pin to be shorted to the CC pins.

These non-ideal equipments and mechanical events make it necessary for the CC pins to be 20-V tolerant, even though they only operate at 5 V or lower. The TPD2S300 enables the CC pins to be 20-V tolerant without interfering with normal operation by providing overvoltage protection on the CC pins. The device places high voltage FETs in series on the CC lines. When a voltage above the OVP threshold is detected on these lines, the high voltage switches are opened up, isolating the rest of the system from the high voltage condition present on the connector.

Finally, most systems require IEC61000-4-2 system level ESD protection for their external pins. The TPD2S300 integrates IEC 61000-4-2 ESD protection for the CC1 and CC2 pins, removing the need to place high voltage TVS diodes externally on the connector.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
TPD2S300 WCSP (9) 1.40 mm × 1.40 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Application Diagram

TPD2S300 TPD2S300_App_Diagram_2_v1.gif

4 Revision History

DATE REVISION NOTES
April 2017 * Initial release.

5 Pin Configuration and Functions

YFF Package
9-Pin WCSP
Top Side Marking View
TPD2S300 Top_Side_Pinout.gif
YFF Package
9-Pin WCSP
Bottom, Bump View
TPD2S300 Bottom_bump_view.gif

Pin Functions

PIN TYPE DESCRIPTION
NO. NAME
A1 C_CC1 I/O Connector side of the CC1 OVP FET. Connect to either CC pin of the USB Type-C connector
A2 VBIAS Power Pin for ESD support capacitor. Place a 0.1-µF capacitor on this pin to ground
A3 C_CC2 I/O Connector side of the CC2 OVP FET. Connect to either CC pin of the USB Type-C connector
B1 CC1 I/O System side of the CC1 OVP FET. Connect to either CC pin of the CC/PD controller
B2 GND GND Ground
B3 CC2 I/O System side of the CC2 OVP FET. Connect to either CC pin of the CC/PD controller
C1 FLT O Open drain for fault reporting
C2 VPWR Power 2.7 V–4.5 V power supply
C3 VM I Voltage mode pin. Place 2.7 V–4.5 V on pin to operate for CC, PD, and FRS. Place 8.7 V–22 V on pin to operate the device in low resistance mode as well

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VI Input voltage VPWR –0.3 5.5 V
VM –0.3 28 V
VO Output voltage FLT –0.3 6 V
VBIAS –0.3 24 V
VIO I/O voltage CC1, CC2 –0.3 6 V
C_CC1, C_CC2 –0.3 24 V
TA Operating free air temperature –40 85 °C
TJ Operating junction temperature –40 105 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings—JEDEC Specification

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±2000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±500 V may actually have higher performance.

6.3 ESD Ratings—IEC Specification

VALUE UNIT
V(ESD) Electrostatic discharge IEC 61000-4-2, C_CC1, C_CC2 Contact discharge ±8000 V
Air-gap discharge ±15000

6.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VI Input voltage VPWR 2.7 3.3 4.5 V
VM 2.7 22 V
VO Output voltage FLT Pull-up resistor power rail 2.7 5.5 V
VIO I/O voltage CC1, CC2, C_CC1, C_CC2 0 5.5 V
IVCONN VCONN current Current flowing from CCx to C_CCx 200 mA
External components(1) FLT Pull-up resistance 1.7 300 kΩ
VBIAS capacitance(2) 0.1 µF
VPWR capacitance, VM capacitance 0.3 1 µF
(1) For recommended values for capacitors and resistors, the typical values assume a component placed on the board near the pin. Minimum and maximum values listed are inclusive of manufacturing tolerances, voltage derating, board capacitance, and temperature variation. The effective value presented must be within the minimum and maximums listed in the table.
(2) The VBIAS pin requires a minimum 35-VDC rated capacitor. A 50-VDC rated capacitor is recommended to reduce capacitance derating. See the VBIAS Capacitor Selection section for more details on VBIAS capacitor selection.

6.5 Thermal Information

THERMAL METRIC(1) TPD2S300 UNIT
YFF (WCSP)
9 PINS
RθJA Junction-to-ambient thermal resistance 107.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 0.9 °C/W
RθJB Junction-to-board thermal resistance 28.1 °C/W
ψJT Junction-to-top characterization parameter 0.5 °C/W
ψJB Junction-to-board characterization parameter 28.2 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.6 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CC OVP SWITCHES
RON_VCONN_1 On resistance of CC OVP FETs VCONN operation VM = 8.7 V, CCx = 3 V, ICCx = 0.6 A,
–40°C ≤ TJ ≤ 105°C		 0.560 Ω
RON_VCONN_2 On resistance of CC OVP FETs VCONN operation VM = 8.7 V, CCx = 4.87 V, ICCx = 0.2 A, –40°C ≤ TJ ≤ 105°C 0.608 Ω
RON_FRS On resistance of CC OVP FETs fast role swap operation VM = 2.7 V, CCx = 0.49 V, ICCx = 30 mA, –40°C ≤ TJ ≤ 105°C 1.3 Ω
RON_CC_ANA On resistance of CC OVP FETs CC analog operation VM = 2.7 V, CCx = 2.45 V, ICCx = 400 µA, –40°C ≤ TJ ≤ 105°C 18.7 Ω
RON_PD On resistance of CC OVP FETs CC USB-PD operation VM = 2.7 V, CCx = 1.2 V, ICCx = 250 µA, –20°C ≤ TJ ≤ 105°C 13 Ω
RONFLAT_VCONN_1 On resistance flatness of CC OVP FETs VCONN operation VM = 8.7 V, sweep CCx from 0 V to 5.5 V, measure the difference in resistance. ICCx = 0.2 A, –40°C ≤ TJ ≤ 105°C 0.2 Ω
CON_CC Equivalent on capacitance for CC pins Capacitance from C_CCx or CCx to GND when device is powered. VC_CCx/VCCx = 0 V to 1.2 V, f = 400 kHz, –40°C ≤ TJ ≤ 105°C 30 120 pF
VTH_DB Threshold voltage of the pull-down FET in series with RD during dead battery I_C_CCx = 80 uA 0.5 0.9 1.2 V
RD Dead battery pull-down resistance (only present when device is unpowered). Effective resistance of RD and FET in series VPWR = 0 V, VC_CCx = 2.6 V 4.1 5.1 6.1 kΩ
VOVPCC_RISE Rising overvoltage protection threshold on C_CCx pins Place 5.5 V on C_CCx pins. Step up voltage until the FLT pin is asserted .–20°C ≤ TJ ≤ 105°C 5.55 6.18 V
VOVPCC_HYS OVP threshold hysteresis Place 6.5 V on C_CCx. Step down the voltage on C_CCx until the FLT pin is deasserted. Measure the difference between rising and falling OVP thresholds 50 mV
BWON On bandwidth single ended (–3dB) Measure the –3-dB bandwidth from C_CCx to CCx. Single ended measurement, 50-Ω system. Vcm = 0 V to 1.2 V 80 MHz
VSTBUS_CC Short-to-VBUS tolerance on the C_CCx pins Hot-Plug C_CCx with a 1 meter USB Type C Cable. Place a 30-Ω load on CCx 24 V
VSTBUS_CC_CLAMP Short-to-VBUS system-side clamping voltage on the CCx pins Hot-Plug C_CCx with a 1-meter USB Type C Cable. Hot-plug voltage C_CCx = 2 4V. VPWR = 3.3 V. Place a 30-Ω load on CCx 8 V
POWER SUPPLY AND LEAKAGE CURRENTS
VPWR_UVLO VPWR undervoltage lockout threshold Place 1 V on VPWR and raise the voltage until the CC FETs turn ON 1.9 2.3 2.55 V
VPWR_UVLO_HYS VPWR UVLO hysteresis Place 3 V on VPWR and lower the voltage until the CC FETs turn off. Calculate the difference between the rising and falling UVLO threshold 50 100 200 mV
IVPWR_1S VPWR quiescent current for 1S battery VPWR = 3.3 V, VM = 3.3 V, C_CCx = 3.6 V, –40°C ≤ TJ ≤ 105°C 3.23 7 µA
IVM_1S VM quiescent current for 1S battery VPWR = 3.3 V, VM = 3.3 V, C_CCx = 3.6 V, –40°C ≤ TJ ≤ 105°C 1 µA
IVPWR_1S_Max VPWR quiescent current for 1S battery max VPWR = 4.5 V, VM = 4.5 V, C_CCx = 3.6 V, –40°C ≤ TJ ≤ 105°C 12 µA
IVM_1S_Max VM quiescent current for 1S battery max VPWR = 4.5 V, VM = 4.5 V, C_CCx = 3.6 V, –40°C ≤ TJ ≤ 105°C 1 µA
IVPWR_3S VPWR quiescent current for 3S battery VPWR = 3.6 V, VM = 13.5 V, C_CCx = 3.6 V, –40°C ≤ TJ ≤ 105°C 8 µA
IVM_3S VM quiescent current for 3S battery VPWR = 3.6 V, VM = 13.5 V, C_CCx = 3.6 V, –40°C ≤ TJ ≤ 105°C 3.5 µA
IVPWR_4S VPWR quiescent current for 4S battery VPWR = 3.6 V, VM = 18 V, C_CCx = 3.6 V, –40°C ≤ TJ ≤ 105°C 8 µA
IVM_4S VM quiescent current for 4S battery VPWR = 3.6 V, VM = 18 V, C_CCx = 3.6 V, –40°C ≤ TJ ≤ 105°C 4.5 µA
ICC_LEAK Leakage current for CC pins when device is powered VPWR = 3.3 V, VM = 3.3 V, VC_CCx = 3.6 V, CCx pins are floating, measure leakage into C_CCx pins. Result must be same if CCx side is biased and C_CCx is left floating 5 µA
IC_CC_LEAK_OVP Leakage current for C_CCx pins when device is in OVP VPWR = VM = 0 V or 3.3 V, VC_CCx = 24 V, CCx = 0 V, measure leakage into C_CCx pins 1500 µA
ICC_LEAK_OVP Leakage current for CCx pins when device is in OVP VPWR = VM = 0 V or 3.3 V, VC_CCx = 24 V, CCx = 0 V, measure leakage flowing out of CCx pins 40 µA
FLT PIN
VOL Low-level output voltage for FLT pin IOL = 3 mA. Measure the voltage at the FLT pin 0.4 V

6.7 Timing Requirements

MIN NOM MAX UNIT
POWER-ON AND POWER-OFF TIMINGS
tON Time from crossing rising VPWR UVLO until CC OVP FETs are on. VPWR slew rate = 0.347 V/µs 200 µs
dVPWR_OFF/dt Minimum slew rate allowed to guarantee CC FETs turn off during a power off –0.5 V/µs
OVERVOLTAGE PROTECTION
tOVP_RESPONSE_CC OVP response time on the CC pins. Time from OVP asserted until OVP FETs turn off. Hot-Plug C_CCx to 24 V with a 1-m cable. C_CCx slew rate = 4 V/ns. Place a 30-Ω on CCx 145 ns
tOVP_RECOVERY_CC OVP recovery time on the CC pins. Time from OVP removal until FET turns back on.VM = 10.8 V. Step C_CCx down from 6.3 V to 3.3 V at a 0.343-V/µs slew rate 30 µs
tOVP_RECOVERY_CC OVP recovery time on the CC pins. Time from OVP removal until FET turns back on.VM = 3.3 V. Step C_CCx down from 6.3 V to 0.49 V at a 0.321-V/µs slew rate 200 µs
tOVP_FLT_ASSERTION Time from OVP asserted to FLT assertion.FLT assertion is when the FLT pin reaches 10% of its starting value. C_CCx from 0 V to 6.3 V at a 0.645-V/µs slew rate 1 µs
tOVP_FLT_DEASSERTION Time from OVP removal to FLT deassertion. FLT deassertion is when the FLT pin reaches 90% of its final value. C_CCx from 6.3 V to 0 V at a 0.696-V/µs slew rate 20 µs

6.8 Typical Characteristics

TPD2S300 D025_SLVSDL1.gif
Figure 1. CC S21 BW
TPD2S300 D012_SLVSDL1.gif
Figure 3. CC Short-to-VBUS 20-V VM = 13 V
TPD2S300 D003_SLVSDL1.gif
Figure 5. CC RON Flatness, VM = 8.7 V
TPD2S300 D017_SLVSDL1.gif
Figure 7. CC RON Flatness, VM = 2.7 V
TPD2S300 D001_SLVSDL1.gif
Figure 9. CC IEC 61000-4-2 8-kV Response Waveform
TPD2S300 D004_SLVSDL1.gif
Figure 11. CC Path Leakage Current vs Ambient Temperature at C_CC = 5.5 V
TPD2S300 D020_SLVSDL1.gif
Figure 13. CC OVP Leakage Current vs Ambient Temperature at C_CC = 24 V
TPD2S300 D005_SLVSDL1.gif
Figure 15. C_CC TLP Curve Unpowered
TPD2S300 D021_SLVSDL1.gif
Figure 17. CC IV Curve
TPD2S300 D010_SLVSDL1.gif
Figure 19. VM Supply Leakage vs Ambient Temperature With C_CC Floating or GND
TPD2S300 D011_SLVSDL1.gif
Figure 2. CC Short-to-VBUS 20-V VM = 3.3 V
TPD2S300 D013_SLVSDL1.gif
Figure 4. CC OVP Recovery VM = 3.3 V
TPD2S300 D016_SLVSDL1.gif
Figure 6. CC RON Flatness, VM = 2.7 V
TPD2S300 D018_SLVSDL1.gif
Figure 8. CC RON Flatness, VM = 2.7 V
TPD2S300 D002_SLVSDL1.gif
Figure 10. CC IEC 61000-4-2 –8-kV Response Waveform
TPD2S300 D019_SLVSDL1.gif
Figure 12. C_CC OVP Leakage Current vs Ambient Temperature at C_CC = 24 V
TPD2S300 D007_SLVSDL1.gif
Figure 14. CC FET Turnon Timing
TPD2S300 D006_SLVSDL1.gif
Figure 16. CC TLP Curve Unpowered
TPD2S300 D009_SLVSDL1.gif
Figure 18. VPWR Supply Leakage vs Ambient Temperature With C_CC Floating or GND

7 Detailed Description

7.1 Overview

The TPD2S300 is a low quiescent current, single chip USB Type-C port protection solution that provides 24-V Short-to-VBUS overvoltage and IEC ESD protection. Due to the small pin pitch of the USB Type-C connector and non-compliant USB Type-C cables and accessories, the VBUS pins can get shorted to the CC pins inside the USB Type-C connector. Because of this Short-to-VBUS event, the CC pins need to be short-to-VBUS tolerant, to support protection on the full USB PD voltage range. Even if a device does not support 20-V operation on VBUS, non complaint adaptors can start out with 20-V VBUS condition, making it necessary for any USB Type-C device to support 20-V protection. Although the USB-PD specification has a maximum VBUS voltage of 21.5 V, non-complaint adaptors could go outside this maximum. Therefore, the TPD2S300 integrates two channels of 24-V Short-to-VBUS overvoltage protection for the CC1 and CC2 pins of the USB Type-C connector.

Additionally, IEC 61000-4-2 system level ESD protection is required in order to protect a USB Type-C port from ESD strikes generated by end product users. The TPD2S300 integrates two channels of IEC61000-4-2 ESD protection for the CC1 and CC2 pins of the USB Type-C connector. Additionally, high voltage IEC ESD protection that is at least 22-V DC tolerant is required for the CC lines in order to simultaneously support IEC ESD and Short-to-VBUS protection (although 24-V DC tolerant is recommended, which the TPD2S300 integrates); there are not many discrete market solutions that can provide this kind of protection. This high-voltage IEC ESD diode is what the TPD2S300 integrates, specifically designed to guarantee it works in conjunction with the overvoltage protection FETs inside the device. This sort of solution is very hard to generate with discrete components.

7.2 Functional Block Diagram

TPD2S300 TPD2S300_Functional_Block_5_v1.gif Figure 20. TPD2S300

7.3 Feature Description

7.3.1 2-Channels of Short-to-VBUS Overvoltage Protection (CC1, CC2 Pins): 24-VDC Tolerant

The TPD2S300 provides 2-channels of Short-to-VBUS Overvoltage Protection for the CC1 and CC2 pins of the USB Type-C connector. The TPD2S300 is able to handle 24-V DC on its C_CC1 and C_CC2 pins. This is necessary because according to the USB PD specification, with VBUS set for 20-V operation, the VBUS voltage is allowed to legally swing up to 21 V, and 21.5 V on voltage transitions from a different USB PD VBUS voltage. The TPD2S300 builds in tolerance up to 24-VBUS to provide margin above this 21.5 V specification to be able to support USB PD adaptors that may break the USB PD specification.

When a short-to-VBUS event occurs, ringing happens due to the RLC elements in the hot-plug event. With very low resistance in this RLC circuit, ringing up to twice the settling voltage can appear on the connector. More than 2x ringing can be generated if any capacitor on the line derates in capacitance value during the short-to-VBUS event. This means that more than 44 V could be seen on a USB Type-C pin during a Short-to-VBUS event. The TPD2S300 has built in circuit protection to handle this ringing. The diode clamps used for IEC ESD protection also clamp the ringing voltage during the short-to-VBUS event to limit the peak ringing to around 30 V. Additionally, the overvoltage protection FETs integrated inside the TPD2S300 are 30-V tolerant, therefore being capable of supporting the high voltage ringing waveform that is experienced during the short-to-VBUS event. The well designed combination of voltage clamps and 30-V tolerant OVP FETs insures the TPD2S300 can handle Short-to-VBUS hot-plug events with hot-plug voltages as high as 24-VDC.

The TPD2S300 has an extremely fast turnoff time of 145 ns typical. Furthermore, additional voltage clamps are placed after the OVP FET on the system side (CC1, CC2) pins of the TPD2S300, to further limit the voltage and current that is exposed to the USB Type-C CC/PD controller during the 145 ns interval while the OVP FET is turning off. The combination of connector side voltage clamps, OVP FETs with extremely fast turnoff time, and system side voltage clamps all work together to insure the level of stress seen on the CC1 and CC2 pin during a short-to-VBUS event is comparable to an HBM ESD event. This is done by design, as any USB Type-C CC/PD controller has built in HBM ESD protection.

7.3.2 2-Channels of IEC61000-4-2 ESD Protection (CC1, CC2 Pins)

The TPD2S300 integrates 2-Channels of IEC 61000-4-2 system level ESD protection for the CC1 and CC2 pins of the USB Type-C connector. USB Type-C ports on end-products need system level IEC ESD protection in order to provide adequate protection for the ESD events that the connector can be exposed to from end users. High-voltage IEC ESD protection that is 24-V DC tolerant is required for the CC lines in order to simultaneously support IEC ESD and Short-to-VBUS protection; there are not many discrete market solutions that can provide this kind of protection. The TPD2S300 integrates this type of high-voltage ESD protection so a system designer can meet both IEC ESD and Short-to-VBUS protection requirements in a single device.

7.3.3 Low Quiescent Current: 3.23 µA (Typical), VPWR, VM = 3.3 V

The TPD2S300 is designed with a very low quiescent current of 3.23 µA (typical) when VPWR = 3.3 V and VM = 3.3 V. The TPD2S300 is designed to have a very low quiescent current to support applications like smart-phones where device battery life is crucial. See the Electrical Characteristics table for complete range of quiescent currents for different VPWR and VM voltages.

7.3.4 CC1, CC2 Overvoltage Protection FETs 200 mA Capable for Passing VCONN Power

The CC pins on the USB Type-C connector serve many functions; one of the functions is to be a provider of power to active cables. Active cables are required when desiring to pass greater than 3 A of current on the VBUS line or when the USB Type-C port uses the super-speed lines (TX1+, TX2–, RX1+, RX1–, TX2+, TX2–, RX2+, RX2–). When CC is configured to provide power, it is called VCONN. VCONN is a DC voltage source in the range of 3 V–5.5 V. If supporting VCONN, a VCONN provider must be able to provide 1 W of power to a cable; this translates into a current range of 200 mA at 5-V VCONN. Therefore, the TPD2S300 has been designed to handle 200 mA of DC current and to have an RON low enough to provide a specification compliant VCONN voltage to the active cable.

7.3.5 CC Dead Battery Resistors Integrated for Handling Dead Battery Use Case in Mobile Devices

An important feature of USB Type-C and USB PD is the ability for this connector to serve as the sole power source to mobile devices. With support up to 100 W, the USB Type-C connector supporting USB PD can be used to power a whole new range of mobile devices not previously possible with legacy USB connectors.

When the USB Type-C connector is the sole power supply for a battery powered device, the device must be able to charge from the USB Type-C connector even when its battery is dead. In order for a USB Type-C power adapter to supply power on VBUS, RD pull-down resistors must be exposed on the CC pins of the sink device. These RD resistors are typically included inside a USB Type-C CC/PD controller. However, when the TPD2S300 is used to protect the USB Type-C port, the OVP FETs inside the device isolates these RD resistors in the CC/PD controller when the mobile device has no power. This is because when the TPD2S300 has no power, the OVP FETs are turned off to guarantee overvoltage protection in a dead battery condition. Therefore, the TPD2S300 integrates high voltage, dead battery RD pull-down resistors to allow dead battery charging simultaneously with high-voltage OVP protection.

When the TPD2S300 is unpowered, and the RP pull-up resistor is connected from a power adaptor, this RP pull-up resistor activates the RD resistor inside the TPD2S300. This enables VBUS to be applied from the power adaptor even in a dead battery condition. Once power is restored back to the system and back to the TPD2S300 on its VPWR pin, the TPD2S300 removes its RD pull-down resistor and turns on its OVP FETs within 200 µs. The amount of time the TPD2S300 does not have either its RD exposed or the PD controller's RD exposed on the CC lines is even less, around 30µs in the worst case, to minimize the probability the USB-C/PD controller in the source device interprets this as a disconnect from the sink. This way connection remains uninterrupted.

If desiring to power the CC/PD controller during dead battery mode and if the CC/PD Controller is configured as a DRP, it is critical that the TPD2S300 be powered before or at the same time that the CC/PD controller is powered. It is also critical that when unpowered, the CC/PD controller also expose its dead battery resistors. When the TPD2S300 gets powered, it exposes the CC pins of the CC/PD controller within 200 µs. Once the TPD2S300 turns on, the RD pull-down resistors of the CC/PD controller must be present immediately, in order to guarantee the power adaptor connected to power the dead battery device keeps its VBUS turned on. If the power adaptor sees the CC voltage go high to the SRC.Open region, it can disconnect VBUS. This removes power from the device with its battery still not sufficiently charged, which consequently removes power from the CC/PD controller and the TPD2S300. Then the RD resistors of the TPD2S300 are exposed again and connect the power adaptor's VBUS to start the cycle over. This creates an infinite loop, never or very slowly charging the mobile device.

If the CC/PD Controller is configured for DRP and has started its DRP toggle before the TPD2S300 turns on, this DRP toggle is unable to guarantee that the power adaptor does not disconnect from the port. Therefore, it is recommended if the CC/PD controller is configured for DRP, that its dead battery resistors be exposed as well, and that they remain exposed until the TPD2S300 turns on. This is typically accomplished by powering the TPD2S300 at the same time as the CC/PD controller when powering the CC/PD controller in dead battery operation.

7.3.6 1.4-mm × 1.4-mm WCSP Package

The TPD2S300 comes in a small, 1.4-mm × 1.4-mm WCSP package, greatly reducing the size of implementing a similar protection solution discretely. Smart-phones and tablets need the smallest package size possible due to the space constraints the PCBs have in these devices.

7.4 Device Functional Modes

Table 1 describes all of the functional modes for the TPD2S300. The "X" in the below table are "do not care" conditions, meaning any value can be present within the absolute maximum ratings of the datasheet and maintain that functional mode.

Table 1. Device Mode Table

Device Mode Table Inputs Outputs
MODE VPWR VM C_CCx FLT CC FETs Dead Battery Resistors
Normal Operating Conditions Unpowered <UVLO X X High-Z OFF ON
Powered on >UVLO ≥VPWR <OVP High-Z ON OFF
Fault Conditions CC overvoltage condition >UVLO ≥VPWR >OVP Low (Fault Asserted) OFF OFF

 
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