Table 2. Design Parameters

8.2.1.2.1 VBIAS Capacitor Selection

As noted in the Recommended Operating Conditions table, a minimum of 35-VBUS rated capacitor is required for the VBIAS pin, and a 50-VBUS capacitor is recommended. The VBIAS capacitor is in parallel with the central IEC diode clamp integrated inside the TPD2S300. A forward biased hiding diode connects the VBIAS pin to the C_CCx pins. Therefore, when a Short-to-V_BUS event occurs at 20 V, 20-V_BUS minus a forward biased diode drop is exposed to the VBIAS pin. Additionally, during the Short-to-V_BUS event, ringing can occur almost double the settling voltage of 20 V, allowing a potential 40 V to be exposed to the C_CCx pins. However, the internal IEC clamps limits the voltage exposed to the C_CCx pins to around 30 V. Therefore, at least 35-VBUS capacitor is required to insure the VBIAS capacitor does not get destroyed during Short-to-V_BUS events.

A 50-V, X7R capacitor is recommended, however. This is to further improve the derating performance of the capacitors. When the voltage across a real capacitor is increased, its capacitance value derates. The more the capacitor derates, the greater than 2x ringing can occur in the Short-to-V_BUS RLC circuit. 50-V X7R capacitors have great derating performance, allowing for the best Short-to-V_BUS performance of the TPD2S300.

Additionally, the VBIAS capacitor helps pass IEC 61000-4-2 ESD strikes. The more capacitance present, the better the IEC performance. So the less the VBIAS capacitor derates, the better the IEC performance. Table 3 shows the real capacitors recommended to achieve the best performance with the TPD2S300.

8.2.1.2.2 Dead Battery Operation

For this application, we want to support 40-W dead battery operation; when the smart-phone is out of battery, we still want to charge the laptop at 20 V and 2 A. This means that the USB PD Controller must receive power in dead battery mode. This means a dead battery LDO must be present in the system to power the TUSB422 and the APU controlling TUSB422 during dead battery. Or, the system PMIC must be able to provide the 1S battery to the APU and TUSB422 during dead battery conditions.

The TPD2S300s OVP FETs remain OFF when it is unpowered in order to insure in a dead battery situation proper protection is still provided to the PD controller or TCPCi in the system, in this case the TUSB422. However, when the OVP FETs are OFF, this isolates the TUSB422's dead battery resistors from the USB Type-C ports CC pins. A USB Type-C power adaptor must see the R_D pull-down dead battery resistors on the CC pins or it does not turn on V_BUS to provide power. Since the TUSB422's dead battery resistors are isolated from the USB Type-C connector's CC pins, the TPD2S300 integrates dead battery resistors on its C_CCx pins. The TPD2S300 exposes these pins when it is unpowered.

Once the power adaptor sees the TPD2S300's dead battery resistors, it applies 5 V on the V_BUS pin. This provides power to the dead battery LDO or PMIC, allowing power to be applied to the APU and TUSB422 to turn them ON, and allowing the battery to begin to charge. However, this application requires 40-W charging in dead battery mode, so V_BUS at 20 V and 2 A is required. USB PD negotiation is required to accomplish this, so the APU through the TUSB422 needs to be able to communicate on the CC pins. This means the TPD2S300 needs to be turned on in dead battery mode as well so the TUSB422 can be exposed to the CC lines. To accomplish this, it is critical that the TPD2S300 is powered by the same dead battery LDO or battery voltage as the APU and TUSB422 during dead battery. This way, the TPD2S300 is turned ON simultaneously with TUSB422.

It is critical that the TUSB422's dead battery resistors are also active on its CC pins for dead battery operation. Once the TPD2S300 receives power, removes its dead battery resistors and turns on its OVP FETs, R_D pull-down resistors must be present on the CC line in order to guarantee the power adaptor stays connected. If RD is not present and the voltage on CC increases into the SRC.Open range, the power adaptor can interpret this as a port disconnect and remove V_BUS.

Once this process has occured, the APU through the TUSB422 can start negotiating with the power adaptor through USB PD for higher power levels, allowing for 40W operation in dead battery mode.

For more information on the TPD2S300 dead battery operation, see the CC Dead Battery Resistors Integrated for Handling Dead Battery Use Case in Mobile Devices section in the description section of the datasheet. Also, see Figure 22 for a waveform of the CC line when the TPD2300 is turning on and exposing R_D dead battery resistors to the USB Type-C connector.

8.2.1.2.3 CC Line Capacitance

USB PD has a specification for the total amount of capacitance that is required for proper USB PD BMC operation on the CC lines. The specification from section 5.8.6 of the USB PD Specification is given in Table 4.

Therefore, the capacitance on the CC lines must stay in between 200 pF and 600 pF when USB PD is being used. Therefore, the combination of capacitances added to the system by the TUSB422, the TPD2S300, and any external capacitor must fall within these limits. Table 5 shows that with TUSB422 + TPD2S300, no external capacitor is required to meet the USB-PD specification.

8.2.1.2.4 FLT Pin Operation

A FLT pin is provided on the TPD2S300 to give the APU the ability to be notified that a Short-to-V_BUS event occured. Once a Short-to-V_BUS occurs on the C_CCx pins, the FLT pin is asserted in 1 µs (typical) so the PD controller can be notified quickly. If V_BUS is being shorted to CC, it is recommended to respond to the event by forcing a detach in the USB PD controller to remove V_BUS from the port. Although the USB Type-C port using the TPD2S300 is not damaged, as the TPD2S300 provides protection from these events, the other device connected through the USB Type-C Cable or any active circuitry in the cable can be damaged. Although shutting the V_BUS off through a detach does not guarantee it stops the other device or cable from being damaged, it can mitigate any high current paths from causing further damage after the initial damage takes place. Additionally, even if the active cable or other device does have proper protection, the Short-to-V_BUS event may corrupt a configuration in an active cable or in the other PD controller, so it is best to detach and reconfigure the port. Therefore, in this application it is recommended that the APU monitor the FLT pin for Short-to-V_BUS faults.

8.2.1.2.5 V_CONN Operation

In our current application example, V_CONN is not required. Therefore, a 3.3-V source or 1S battery can be connected to the VPWR and VM pins of the TPD2S300 and provide adaqute resistance in order to support CC analog and USB PD operation over the CC lines. In fact, the CC OVP FETs resistance specifications are set to optimize the FET size and therefore the TPD2S300 size and still allow proper CC analog and USB PD operation. See the Electrical Characteristics table for the specific resistances of the CC OVP FETs.

8.2.1.2.6 Low Quiescent Current

Smart-Phone applications require low quiescent current to meet long battery life specifications to provide the best experience to end-users. The TPD2S300 is designed to have very low quiescent current in order to meet these requirements. The lower the voltage kept on the C_CCx lines, and the lower the voltage kept on the VPWR and VM pins, the lower the quiescent current is on the TPD2S300. If an LDO is used that keeps VPWR and VM limited to 3.3 V, then the maximum quiescent current on VPWR is 7 µA, and the maximum current on VM is 1 µA. If the 1S battery is connected to the VPWR and VM pins, such that the maximum voltage applied to VPWR and VM is 4.5 V, then the maximum quiescent current is going to be 12 µA for VPWR, and VM has 1 µA maximum. Therefore, our application can achieve a very low total quiescent current for protection with the TPD2S300, between 8 µA and 13 µA, depending on how the TPD2S300 is powered. For all details on quiescent current values, see the Electrical Characteristics table.

Table 6. Design Parameters

8.2.2.2.1 VBIAS Capacitor Selection

This VBIAS capacitor requirements for this application are identical to the Smart-Phone application; see the VBIAS Capacitor Selection section for more details.

8.2.2.2.2 Dead Battery Operation

For this application, we want to support 100-W dead battery operation; when the laptop is out of battery, we still want to charge the laptop at 20 V and 5 A. This means that the USB PD Controller must receive power in dead battery mode. The TPS65987 has its own built in LDO in order to supply the TPS65987 power from V_BUS in a dead battery condition. The TPS65987 can also provide power to its flash during this condition through its LDO_3V3 pin.

The TPD2S300s OVP FETs remain OFF when it is unpowered in order to insure in a dead battery situation proper protection is still provided to the PD controller in the system, in this case the TPS65987. However, when the OVP FETs are OFF, this isolates the TPS65987's dead battery resistors from the USB Type-C ports CC pins. A USB Type-C power adaptor must see the R_D pull-down dead battery resistors on the CC pins or it does not turn ON V_BUS to provide power. Since the TPS65987s dead battery resistors are isolated from the USB Type-C connector's CC pins, the TPD2S300 integrates dead battery resistors on its C_CCx pins, and exposes them when the device is unpowered.

Once the power adaptor sees the TPD2S300's dead battery resistors, it applies 5 V on the V_BUS pin. This provides power to the TPS65987, turning the PD controller on, and allowing the battery to begin to charge. However, this application requires 100-W charging in dead battery mode, so V_BUS at 20 V and 5 A is required. USB PD negotiation is required to accomplish this, so the TPS65987 needs to be able to communicate on the CC pins. This means the TPD2S300 needs to be turned on in dead battery mode as well so the TPD65987's PD controller can be exposed to the CC lines. To accomplish this, it is critical that the TPD2S300 is powered by the TPS65987's internal LDO, the LDO_3V3 pin. This way, when the TPS65987 receives power on V_BUS, the TPD2S300 is turned on simultaneously. Additionally, for low resistance VCONN support, the VM pin needs to be connected to the 3S battery, so TPD2S300 needs to be able to receive this voltage in the dead battery condition as well.

It is critical that the TPS65987's dead battery resistors are present; once the TPD2S300 receives power, removes its dead battery resistors and turns on its OVP FETs, R_D pull-down resistors must be present on the CC line in order to guarantee the power adaptor stays connected. If RD is not present and the voltage on CC increases to Src.Open, the power adaptor can interpret this as a disconnect and remove V_BUS.

Also, it is important that the TPS65987's dead battery resistors are present so it properly boots up in dead battery operation with the correct voltages on its CC pins.

Once this process has occurred, the TPS65987 can start negotiating with the power adaptor through USB PD for higher power levels, allowing 100-W operation in dead battery mode.

For more information on the TPD2S300 dead battery operation, see the CC Dead Battery Resistors Integrated for Handling Dead Battery Use Case in Mobile Devices section in the description section of the datasheet. Also, see Figure 22 for a waveform of the CC line when the TPD2S300 is turning on and exposing the TPS65987's dead battery resistors to the USB Type-C connector.

8.2.2.2.3 CC Line Capacitance

USB PD has a specification for the total amount of capacitance that is required for proper USB PD BMC operation on the CC lines. The specification from section 5.8.6 of the USB PD Specification is given in Table 4.

Therefore, the capacitance on the CC lines must stay in between 200 pF and 600 pF when USB PD is being used. Therefore, the combination of capacitances added to the system by the TPS65987, the TPD2S300, and any external capacitor must fall within these limits. Table 5 shows the analysis involved in choosing the correct external CC capacitor for this system, and shows that an external CC capacitor is required.

8.2.2.2.4 FLT Pin Operation

This FLT pin recommendation for this application are identical to the Smart-Phone application; see the FLT Pin Operation section for more details.

8.2.2.2.5 V_CONN Operation

In our current application example, 1-W V_CONN is required. With a 5-V source on the TPS65987's PP_CABLE pin, this means 200 mA of current is required. Therefore, it is ideal to put the TPD2S300 in low-resistance mode, which is easy to do in this application because of the presence of a 3S battery in the laptop. Tie the VM pin to the 3S battery voltage. With the VM pin tied to the 3S battery, the worst case resistance of TPD2S300 with 4.87 V on CCx is 608 mΩ. This way with 200 mA flowing through the TPD2S300, voltage drop is much lower across the TPD2S300 and it is easier to achieve the VCONN voltage requirements given in the USB Type-C Specification.

Table 9. Design Parameters

8.2.3.2.1 VBIAS Capacitor Selection

This VBIAS capacitor requirements for this application are identical to the Smart-Phone application; please see the VBIAS Capacitor Selection section for more details.

8.2.3.2.2 Dead Battery Operation

This application is source mode only. Therefore, dead battery operation is not required, and R_D resistors must not be exposed on the CC lines. However, because when the TPD2S300 is unpowered it exposes its dead battery resistors, when the wall adaptor is not plugged into the wall, it has RDs present on its CC lines. If it is plugged into a laptop at this point, then the laptop senses a connection and output 5-V V_BUS. Therefore, the power switch that sources V_BUS in the wall adaptor must be able to block this 5-V V_BUS from entering the system when it is unplugged from the wall. If this is maintained, there is not any issue. Once, the wall adaptor is plugged into the wall, it turns ON the TPD2S300. This removes the TPD2S300's RD dead battery resistor, and then the laptop stops sourcing V_BUS. Once the laptop starts its DRP toggle, it exposes its RD, which causes a connection with the wall adaptor to occur, and the wall adaptor outputs V_BUS, and then PD is negotiated like normal.

8.2.3.2.3 CC Line Capacitance

USB PD has a specification for the total amount of capacitance that is required for proper USB PD BMC operation on the CC lines. The specification from section 5.8.6 of the USB PD Specification is given in Table 10.

Therefore, the capacitance on the CC lines must stay in between 200 pF and 600 pF when USB PD is being used. Therefore, the combination of capacitances added to the system by the TPS25740, the TPD2S300, and any external capacitor must fall within these limits. Table 11 shows the analysis involved in choosing the correct external CC capacitor for this system, and shows that an external CC capacitor is required.

8.2.3.2.4 FLT Pin Operation

The FLT pin recommendation for this application are identical to the Smart-Phone application; see the FLT Pin Operation section for more details.

8.2.3.2.5 V_CONN Operation

In our current application example, V_CONN is not required. Therefore, a 3.3-V source or 5-V source can be connected to the VPWR and VM pins of the TPD2S300 to provide adequate resistance in order to support CC analog and USB PD operation over the CC lines. In fact, the CC OVP FETs resistance specifications are set to optimize the FET size and therefore the TPD2S300 size and still allow proper CC analog and USB PD operation. See the Electrical Characteristics table for the specific resistances of the CC OVP FETs.