SLLSEY0A April   2017  – July 2017 TPD2S701-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings—AEC Specification
    3. 6.3  ESD Ratings—IEC Specification
    4. 6.4  ESD Ratings—ISO Specification
    5. 6.5  Recommended Operating Conditions
    6. 6.6  Thermal Information
    7. 6.7  Electrical Characteristics
    8. 6.8  Power Supply and Supply Current Consumption Chracteristics
    9. 6.9  Timing Requirements
    10. 6.10 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 OVP Operation
      2. 8.3.2 OVP Threshold
      3. 8.3.3 D± Clamping Voltage
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Device Operation
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 VREF Operation
          1. 9.2.2.1.1 Mode 0
          2. 9.2.2.1.2 Mode 1
        2. 9.2.2.2 Mode 1 Enable Timing
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 VPWR Path
    2. 10.2 VREF Pin
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Detailed Description

8.1 Overview

The TPD2S701-Q1 is a 2-Channel Data Line Short-to-VBUS and IEC61000-4-2 ESD protection device for automotive high-speed interfaces like USB2.0. The TPD2S701-Q1 contains two data line nFET switches which ensure safe data communication while protecting the internal system circuits from any overvoltage conditions at the VD+ and VD– pins. On these pins, this device can handle overvoltage protection up to 7-V DC. This provides sufficient protection for shorting the data lines to the USB VBUS rail.

Additionally, the TPD2S701-Q1 has a FLT pin which provides an indication when the device sees an overvoltage condition and automatically resets when the overvoltage condition is removed. The TPD2S701-Q1 also integrates IEC ESD clamps on the VD+ and VD– pins, thus eliminating the need for external TVS clamp circuits in the application.

The TPD2S701-Q1 has an internal oscillator and charge pump that controls the turnon of the internal nFET switches. The internal oscillator controls the timers that enable the charge pump and resets the open-drain FLT output. If VD+ and VD– are less than VOVP, the internal charge pump is enabled. After an internal delay, the charge-pump starts-up, turning on the internal nFET switches. At any time, if VD+ or VD– rises above VOVP, TPD2S701-Q1 asserts FLT pin LOW and the nFET switches are turned off.

8.2 Functional Block Diagram

TPD2S701-Q1 Function_Block.gif

8.3 Feature Description

8.3.1 OVP Operation

When the VD+, or VD– voltages rise above VOVP, the internal nFET switches are turned off, protecting the transceiver from overvoltage conditions. The response is very rapid, with the FET switches turning off in less than 1 µs. Before the OVP condition, the FLT pin is High-Z, and is pulled HIGH via an external resistor to indicate there is no fault. Once the OVP condition occurs, the FLT pin is asserted LOW. When the VD+, or VD– voltages returns below VOVP – VHYS-OVP, the nFET switches are turned on again. When the OVP condition is cleared and the nFETs are completely turned on, the FLT is reset to high-Z.

8.3.2 OVP Threshold

TPD2S701-Q1 tpd2S-ovp-diagram.gif Figure 20. OVP Threshold

The OVP Threshold VOVP is set by VREF according to Equation 1, Equation 2 and Equation 3.

Equation 1. TPD2S701-Q1 OVP_Th_Equation_1.gif
Equation 2. TPD2S701-Q1 OVP_Th_Equation_2.gif
Equation 3. TPD2S701-Q1 OVP_Th_Equation_3.gif

Equation 1, Equation 2 and Equation 3 yield the typical VOVP values. See the parametric tables for the minimum and maximum values that include variation over temperature and process. Figure 20 gives a graphical representation of the relationship between VOVP and VREF.

VREF can be set either by an external regulator (Mode 0) or an internal adjustable regulator (Mode 1). See the VREF Operation section for more details on how to operate VREF in Mode 0 and Mode 1.

8.3.3 D± Clamping Voltage

The TPD2S701-Q1 provides a differentiated device architecture which allows the system designer to control the clamping voltage the protected transceiver sees from the D+ and D– pins. This architecture allows the system designer to minimize the amount of stress the transceiver sees during ESD events. The clamping voltage that appears on the D+ and D– lines during an ESD event obeys Equation 4.

Equation 4. TPD2S701-Q1 Equation_3.gif

Where VBR approximately = 0.7 V, IRDYN approximately = 1 V. By adjusting VREF, the clamping voltage of the D+ and D– lines can be adjusted. As VREF also controls the OVP threshold, take care to insure that the VREF setting both satisfies the OVP threshold requirements while simultaneously optimizing system protection on the D+ and D– lines.

The size of the capacitor used on the VREF pin also influences the clamping voltage as transient currents during ESD events flow into the VREF capacitor. This causes the VREF voltage to increase, and likewise the clamping voltage on D± according to Equation 4. The larger capacitor that is used, the better the clamping performance of the device is going to be. See the parametric tables for the clamping performance of the TPD2S701-Q1 with a 1-µF capacitor.

8.4 Device Functional Modes

The TPD2S701-Q1 has two modes of operation which vary the way the VREF pin functions. In Mode 0, the VREF pin is connected to an external regulator which sets the voltage on the VREF pin. In Mode 1, the TPD2S701-Q1 uses an adjustable internal regulator to set the VREF voltage. Mode 1 enables the system designer to operate the TPD2S701-Q1 with a single power supply, and have the flexibility to easily set the VREF voltage to any voltage between 0.6 V and 3.8 V with two external resistors.