SLVSCG4C January 2016 – August 2020 TPD3S714-Q1
PRODUCTION DATA
When the VD+, VD–, or VBUS_CON pins exceed their OVP threshold, the device enters the overvoltage state. All FETs are disabled and the FLT pin is asserted. Once the protected pins drop below their OVP threshold, the device automatically turns back on.