SLLS682O July   2006  – July 2019 TPD4E001

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Application Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings—JEDEC Specification
    3. 6.3 ESD Ratings—IEC Specification
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

DRL Package
6-Pin SOT
Top View
TPD4E001 po_DRL_slls682.gif
DCK2 Package
6-Pin SC70
Top View
TPD4E001 po_DCK2_slls682_updated.gif
DBV or DCK Package
6-Pin SOT or SC70
Top View
TPD4E001 po_DBV_DCK_slls682.gif
DRS Package
6-Pin SON
Top View
TPD4E001 po_QFN_slls682.gif
DPK Package
6-Pin USON
Top View
TPD4E001 po_DPK_slls682.gif
TPD4E001R DBV Package
6-Pin SOT
Top View
TPD4E001 slls682-dbv-pin-drawing.gif

Pin Functions

PIN I/O DESCRIPTION
NAME DRS, DRL, DPK DBV, DCK TPD4E001R
GND 3 2 5 — Ground
IOx 1 1 1 I ESD-protected channel
2 3 3
4 4 4
5 6 6
VCC 6 5 2 I Power-supply input. Bypass VCC to GND with a 0.1-μF ceramic capacitor
Exposed thermal
pad (DRS package only) 		— Exposed thermal pad. Connect to GND or leave floating