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  • TPD4E002 Quad Low-Capacitance Array with ±15-kV ESD Protection

    • SLVS615F July   2006  – December 2016 TPD4E002

      PRODUCTION DATA.  

  • CONTENTS
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  • TPD4E002 Quad Low-Capacitance Array with ±15-kV ESD Protection
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings—JEDEC Specification
    3. 6.3 ESD Ratings—IEC Specification
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Signal Range on I/O1 Through I/O2
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
  13. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • DRL|5
    • MPDS158G
Thermal pad, mechanical data (Package|Pins)
Orderable Information
  • slvs615f_oa
  • slvs615f_pm
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DATA SHEET

TPD4E002 Quad Low-Capacitance Array with ±15-kV ESD Protection

1 Features

  • IEC 61000-4-2 ESD Protection
    • ±15-kV IEC 61000-4-2 Contact Discharge
  • IEC 61000-4-5 Surge Protection
    • 2.5-A Peak Pulse Current (8/20-µs Pulse)
  • ANSI/ESDA/JEDEC JS-001
    • ±15-kV Human Body Model (HBM)
  • Four Unidirectional Voltage Suppression Diodes for use in ESD Protection
  • I/O Breakdown Voltage, VBR = 6.1 V (Minimum)
  • I/O Capacitance 11 pF (Typical)
  • Low Leakage Current < 100 nA
  • Very Small Printed-Circuit Board (PCB) Area
    < 2.6 mm2
  • High Integration
  • Suitable for High-Density Boards

2 Applications

  • Computers
  • Printers
  • Communication Systems and Cellular Phones
  • Video Equipment

3 Description

The TPD4E002 device is a transient voltage suppressor (TVS) designed to protect up to four lines against electrostatic discharge (ESD) transients. The monolithic circuit design allows superior capacitance matching between the channels and reduced crosstalk. This device is ideal for applications where both reduced line capacitance and board space-saving are required.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
TPD4E002 SOT (5) 1.60 mm × 1.20 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Application Schematic

TPD4E002 App_Schem.gif

4 Revision History

Changes from E Revision (February 2016) to F Revision

  • Updated the Pin Functions tableGo

Changes from D Revision (July 2010) to E Revision

  • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information sectionGo
  • Deleted Ordering Information table. See POA at the end of the documentGo

5 Pin Configuration and Functions

DRL Package
5-Pin SOT
Top View
TPD4E002 Package.gif

Pin Functions

PIN TYPE DESCRIPTION
NO. NAME
1 I/O1 I/O ESD protection channel
2 GND — Ground
3 I/O2 I/O ESD protection channel
4 I/O3 I/O ESD protection channel
5 I/O4 I/O ESD protection channel

 
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