SLVSDZ2A June   2017  – September 2017 TPD4E02B04-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings—AEC Specification
    3. 6.3 ESD Ratings—IEC Specification
    4. 6.4 ESD Ratings—ISO Specification
    5. 6.5 Recommended Operating Conditions
    6. 6.6 Thermal Information
    7. 6.7 Electrical Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  AEC-Q101 Qualified
      2. 7.3.2  ISO 10605 ESD Protection
      3. 7.3.3  IEC 61000-4-2 ESD Protection
      4. 7.3.4  IEC 61000-4-4 EFT Protection
      5. 7.3.5  IEC 61000-4-5 Surge Protection
      6. 7.3.6  IO Capacitance
      7. 7.3.7  DC Breakdown Voltage
      8. 7.3.8  Ultra Low Leakage Current
      9. 7.3.9  Low ESD Clamping Voltage
      10. 7.3.10 Supports High Speed Interfaces
      11. 7.3.11 Industrial Temperature Range
      12. 7.3.12 Easy Flow-Through Routing Package
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Signal Range
        2. 8.2.2.2 Operating Frequency
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Electrical fast transient IEC 61000-4-5 (5/50 ns) at 25°C 80 A
Peak pulse IEC 61000-4-5 power (tp - 8/20 µs) at 25°C 17 W
IEC 61000-4-5 Ccurrent (tp - 8/20 µs) at 25°C 2 A
TA Operating free-air temperature –40 125 °C
Tstg Storage temperature –65 155 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings—AEC Specification

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±2500 V
Charged-device model (CDM), per AEC Q100-011 ±1000
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 ESD Ratings—IEC Specification

VALUE UNIT
V(ESD) Electrostatic discharge IEC 61000-4-2 contact discharge ±12000 V
IEC 61000-4-2 air-gap discharge ±15000

6.4 ESD Ratings—ISO Specification

VALUE UNIT
V(ESD) Electrostatic discharge ISO 10605 330 pF, 330 Ω, IO Contact discharge ±10000 V
Air-gap discharge ±10000

6.5 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VIO Input pin voltage –3.6 3.6 V
TA Operating free-air temperature –40 125 °C

6.6 Thermal Information

THERMAL METRIC(1) TPD4E02B04-Q1 UNIT
DQA (USON)
10 PINS
RθJA Junction-to-ambient thermal resistance 348.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 214.1 °C/W
RθJB Junction-to-board thermal resistance 270.7 °C/W
ψJT Junction-to-top characterization parameter 81.7 °C/W
ψJB Junction-to-board characterization parameter 270.7 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.7 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VRWM Reverse stand-off voltage IIO < 10 nA –3.6 3.6 V
VBRF Breakdown voltage, any IO pin to GND(1) IIO = 1 mA, TA = 25°C 5.5 6.4 7.5 V
VBRR Breakdown voltage, GND to any IO pin(1) IIO = 1 mA, TA = 25°C –5.5 –6.4 –7.5 V
VHOLD Holding voltage(2) IIO = 1 mA 5.8 V
VCLAMP Clamping voltage IPP = 1 A, TLP, from IO to GND 6.6 V
IPP = 5 A, TLP, from IO to GND 8.8
IPP = 1 A, TLP, from GND to IO 6.6
IPP = 5 A, TLP, from GND to IO 8.8
ILEAK Leakage current, any IO to GND VIO = ±2.5 V 10 nA
RDYN Dynamic resistance IO to GND 0.47 Ω
GND to IO 0.47
CL Line capacitance VIO = 0 V, f = 1 MHz, IO to GND, TA = 25°C 0.25 0.33 pF
ΔCL Variation of line capacitance Delta of capacitance between any two IO pins, VIO = 0 V, f = 1 MHz, TA = 25°C, GND = 0 V 0.01 0.07 pF
CCROSS Channel to channel capacitance Capacitance from one IO to another, VIO = 0 V, f = 1 MHz, GND = 0 V 0.13 0.16 pF
(1) VBRF and VBRR are defined as the voltage when 1 mA is applied in the positive-going direction, before the device latches into the snapback state.
(2) VHOLD is defined as the voltage when 1 mA is applied in the negative-going direction, after the device has successfully latched into the snapback state.

6.8 Typical Characteristics

TPD4E02B04-Q1 C001_SLVSD85.png
Figure 1. Positive TLP Curve
TPD4E02B04-Q1 D004_SLVSD85.gif
Figure 3. Surge Curve (tp = 8/20 µs), any IO pin to GND
TPD4E02B04-Q1 D006_SLVSD85.gif
Figure 5. –8-kV IEC Waveform
TPD4E02B04-Q1 D008_SLVSD85.gif
Figure 7. Capacitance vs Ambient Temperature
TPD4E02B04-Q1 D010_SLVSD85.gif
Figure 9. DC Voltage Sweep I-V Curve
TPD4E02B04-Q1 D012_SLVSD85.gif
Figure 11. 8-kV IEC Waveform through 2-m HDMI Cable
TPD4E02B04-Q1 5gbps_bare_board.png
Figure 13. USB3.0 Eye Diagram (Bare Board)
TPD4E02B04-Q1 Figures 15 and 22-unpopulated.png
Figure 15. USB3.1 Gen 2 Eye Diagram (Bare Board)
TPD4E02B04-Q1 6gbps_bare_board.png
Figure 17. HDMI2.0 6-Gbps TP2 Eye Diagram (Bare Board)
TPD4E02B04-Q1 D014_SLVSD85.gif
Figure 19. Differential Insertion Loss
TPD4E02B04-Q1 C002_SLVSD85.png
Figure 2. Negative TLP Curve
TPD4E02B04-Q1 D005_SLVSD85.gif
Figure 4. 8-kV IEC Waveform
TPD4E02B04-Q1 D007_SLVSD85.gif
Figure 6. Capacitance vs Bias Voltage
TPD4E02B04-Q1 D009_SLVSD85.gif
Figure 8. Leakage Current vs Temperature
TPD4E02B04-Q1 D011_SLVSD85.gif
Figure 10. Capacitance vs Frequency
TPD4E02B04-Q1 D013_SLVSD85.gif
Figure 12. –8-kV IEC Waveform through 2-m HDMI Cable
TPD4E02B04-Q1 5gbps_populated.png
Figure 14. USB3.0 Eye Diagram (With TPD4E02B04-Q1)
TPD4E02B04-Q1 Figures 16 and 23-populated.png
Figure 16. USB3.1 Gen 2 Eye Diagram
(With TPD4E02B04-Q1)
TPD4E02B04-Q1 6gbps_populated.png
Figure 18. HDMI2.0 6-Gbps TP2 Eye Diagram (With TPD4E02B04-Q1)