SLVSC54B July   2013  – April 2014 TPD4E110

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Terminal Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Signal range on Terminal 1, 2, 3, or 4
        2. 9.2.2.2 Operating Frequency
      3. 9.2.3 Application Curves
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Single Layer Routing
      2. 10.2.2 Double Layer Routing
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Provides System Level ESD Protection for Low-Voltage IO Interface
  • IO Capacitance 0.45pF (Typ)
  • IEC 61000-4-2 Level 4
    • ±12kV (Contact Discharge)
    • ±15kV (Air Gap Discharge)
  • IEC61000-4-5 (Surge): 2.5A (8/20 µs)
  • DC Breakdown Voltage 6.5V (Min)
  • Ultra Low Leakage Current 1nA (Max)
  • Low ESD Clamping Voltage
  • Industrial Temperature Range: –40°C to 125°C
  • Space Minimizing 0.8mm x 0.8mm DPW Package

2 Applications

  • USB 3.0
  • HDMI 2.0
  • LVDS
  • DisplayPort
  • PCI Express
  • eSata Interfaces

3 Description

The TPD4E110 is a uni-directional Electrostatic Discharge (ESD) protection device with ultra-low capacitance. The device is constructed with a central ESD clamp and features two hiding diodes per channel to reduce the capacitive loading. Each channel is rated to dissipate ESD strikes above the maximum level specified in the IEC61000-4-2 level 4 international standard. The TPD4E110's ultra-low loading capacitance makes the device ideal for protecting high-speed signal pins.

Device Information

ORDER NUMBER PACKAGE BODY SIZE
TPD4E110DPW X2SON (4) 0,8 mm x 0,8 mm

Circuit Protection Scheme

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4 Simplified Schematic

cir_prot_slvsc54.gif

Insertion Loss

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