SLVSAC2G
August 2010 – June 2021
TPD2EUSB30
,
TPD2EUSB30A
,
TPD4EUSB30
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagrams
7.3
Feature Description
7.4
Device Functional Modes
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
Signal Range on D+, D- Pins
8.2.2.2
Operating Frequency
8.2.3
Application Curves
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.2
Layout Examples
11
Device and Documentation Support
11.1
Receiving Notification of Documentation Updates
11.2
Support Resources
11.3
Trademarks
11.4
Electrostatic Discharge Caution
11.5
Glossary
12
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
DQA|10
MPSS004C
Thermal pad, mechanical data (Package|Pins)
DQA|10
QFND791
Orderable Information
slvsac2g_oa
slvsac2g_pm
6.6
Typical Characteristics
T
A
= 25 °C
Figure 6-1
IO Capacitance vs IO Voltage
Measured at one IO, the other IO open
Figure 6-3
Peak Pulse Waveforms
Figure 6-5
IEC Clamping Waveforms (8 kV Contact)
–3 dB = 7.4 Gbps
Figure 6-7
Insertion Loss
V
IO
= 2.5 V
Figure 6-2
Leakage Current vs Temperature
Figure 6-4
D+,D– Transmission Line Pulser Plot for TPD2EUSB30 (100 ns Pulse, 10 ns Rise Time)
Figure 6-6
IEC Clamping Waveforms (–8 kV Contact)