SLVS928B March   2009  – August 2014 TPD4S012

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configurations and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Integrated ESD Clamps
      2. 7.3.2 USB Signal Pins
      3. 7.3.3 VBUS Line
      4. 7.3.4 Supports Data Rates in Excess of 480 Mbps
      5. 7.3.5 IEC 61000-4-2 (Level 4 Contact)
      6. 7.3.6 IEC 61000-4-5 Surge
    4. 7.4 Device Functional Modes
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Signal Range on D+, D-, ID and VBUS pins
        2. 8.2.2.2 Operating Frequency
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)
PARAMETER MIN MAX UNIT
VBUS voltage tolerance VBUS pin –0.3 20 V
IO voltage tolerance D+, D–, ID pins –0.3 6 V
TA Operating free-air temperature range –40 85 °C
IEC 61000-4-2 Contact Discharge D+, D–, ID ±10 kV
VBUS pin ±10 kV
IEC 61000-4-2 Air-Gap Discharge D+, D–, ID ±10 kV
VBUS pin ±9 kV
IEC 61000-4-5 Surge (tp = 8/20 μs) Peak pulse Power (All pins) 60 W
Peak pulse current (All Pins) 3 A

6.2 Handling Ratings

MIN MAX UNIT
Tstg Storage temperature range –65 125 °C
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) –2.5 2.5 kV
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) –1 1
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
PARAMETER MIN MAX UNIT
TA Operating free-air Temperature Range –40 85 °C
Operating Voltage VBUS Pin 0 15 V
D+, D–, ID Pins 0 5.5

6.4 Thermal Information

THERMAL METRIC(1) TPD4S012 UNIT
DRY
6 PINS
RθJA Junction-to-ambient thermal resistance 461.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 219.6
RθJB Junction-to-board thermal resistance 343.7
ψJT Junction-to-top characterization parameter 162.5
ψJB Junction-to-board characterization parameter 343.7
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IVBUS VBUS operating current VBUS = 19 V D+, D–, ID pins open 0.1 0.5 μA
IIO IO port current VIO = 2.5 V, VBUS = 5 V D+, D–, ID pins 0.1 0.5 μA
VD Diode forward voltage IIO = 8 mA D+, D–, ID pins (lower clamp diode) 0.6 0.8 0.95 V
CVBUS VBUS pin capacitance VBUS = 5 V 11 15 pF
CIO IO capacitance VIO = 2.5 V D+, D–, ID pins 0.8 1 pF
RDYN Dynamic resistance IIO = 1.5 A D+, D–, ID, and VBUS pins, including central clamp dioded during positive ESD pulse 1.2 Ω
IIO = 1 A D+, D–, ID, and VBUS pins, including central clamp diode during negative ESD pulse 1
VBR Breakdown voltage IIO = 1 mA D+, D–, ID pins 6 9 V
VBUS pin(s) 20 24

6.6 Typical Characteristics

g_did_pkplswaveform_lvs928.gifFigure 1. Peak Pulse Power Waveform at the D+, D–, or ID Pin
g_esdclampvol_did_lvs928.gifFigure 3. D+, D–, or ID Clamp Voltage Under ESD Event
g_didpincapacitance_lvs928.gifFigure 5. D+, D–, or ID Capacitance, TA = 27°C
g_iecclamp_plus8kv_lvs928.gifFigure 7. IEC Clamping Waveform, 8 kV Contact, D+, 25 ns/div
g_vbusiecclamp_plus8kv_lvs928.gifFigure 9. VBUS IEC Clamping Waveform, 8 kV Contact, 25 ns/div
g_vbus_pkplswaveform_lvs928.gifFigure 2. Peak Pulse Power Waveform at the VBUS Pin
g_esdclampvol_vbus_lvs928.gifFigure 4. VBUS Clamp Voltage Under ESD Event
g_vbuscapacitance_lvs928.gifFigure 6. VBUS Capacitance, TA = 27°C
g_iecclamp_neg8kv_lvs928.gifFigure 8. IEC Clamping Waveform, –8 kV Contact, D+, 25 ns/div
g_vbusiecclamp_neg8kv_lvs928.gifFigure 10. VBUS IEC Clamping Waveform, –8 kV Contact, 25 ns/div