SLVSAU0G May   2011  – December 2015 TPD4S014

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics, EN, ACK, D+, D-, ID Pins
    6. 6.6 Electrical Characteristics OVP Circuits
    7. 6.7 Supply Current Consumption
    8. 6.8 Thermal Shutdown Feature
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Voltage Protection at VBUS up to 28 V DC
      2. 7.3.2 Low RON nFET Switch
      3. 7.3.3 ESD Performance D+/D-/ID/VBUS Pins
      4. 7.3.4 Overvoltage and Undervoltage Lockout Features
      5. 7.3.5 Capacitance TVS ESD Clamp for USB2.0 Hi-Speed Data Rate
      6. 7.3.6 Start-up Delay
      7. 7.3.7 OVP Glitch Immunity
      8. 7.3.8 Integrated Input Enable and Status Output Signal
      9. 7.3.9 Thermal Shutdown
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 For Non-OTG USB Systems
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 For OTG USB Systems
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPD4S014 is a single-chip solution for USB charger port protection. This device offers low capacitance TVS type ESD clamps for the D+, D–, and standard capacitance for the ID pin. On the VBUS pin, this device can handle over voltage protection up to 28 V. The over voltage lockout feature ensures that if there is a fault condition at the VBUS line TPD4S014 is able to isolate the VBUS line and protect the internal circuitry from damage. In order to let the voltage stabilize before closing the switch there is a 17 ms turn on delay after VBUS crosses the UVLO threshold. This function acts as a de-glitch which prevents unnecessary switching if there is any ringing on the line during connection. Due to the body diode of the nFET switch, if there is a short to ground on VBUS the system is expected to limit the current to VBUSOUT.

8.2 Typical Applications

8.2.1 For Non-OTG USB Systems

TPD4S014 app_dia_lvsau0.gif Figure 12. Non-OTG Schematic

8.2.1.1 Design Requirements

Table 2 shows the design parameters.

Table 2. Design Parameters

DESIGN PARAMETERS EXAMPLE VALUE
Signal range on VBUS 3.3 V – 5.9 V
Signal range on VBUSOUT 3.9 V – 5.9 V
Signal range on D+/D– and ID 0 V – 5 V
Drive EN low (enabled) 0 V – 0.5 V
Drive EN high (disabled) 1 V – 6 V

8.2.1.2 Detailed Design Procedure

To begin the design process, some parameters must be decided upon. The designer needs to know the following:

  • VBUS voltage range
  • Processor logic levels VOH, VOL for EN and VIH, VIL for ACK pins

8.2.1.3 Application Curves

TPD4S014 typ_eye1_lvsau0.png Figure 13. Eye Diagram With No EVM and No IC, Full USB2.0 Speed at 480 Mbps
TPD4S014 typ_eye3_lvsau0.png Figure 15. Eye Diagram With EVM and IC, Full USB2.0 Speed at 480 Mbps
TPD4S014 typ_eye2_lvsau0.png Figure 14. Eye Diagram With EVM, No IC, Full USB2.0 Speed at 480 Mbps

8.2.2 For OTG USB Systems

TPD4S014 app2_dia_lvsau0.gif Figure 16. OTG Schematic

8.2.2.1 Design Requirements

Table 3 shows the design parameters.

Table 3. Design Parameters

DESIGN PARAMETERS EXAMPLE VALUE
Signal range on VBUS 3.3 V – 5.9 V
Signal range on VBUSOUT 3.9 V – 5.9 V
Signal range on D+/D– and ID 0 V – 5 V
Drive EN low (enabled) 0 V – 0.5 V
Drive EN high (disabled) 1 V – 6 V

8.2.2.2 Detailed Design Procedure

To begin the design process, some parameters must be decided upon. The designer needs to know the following:

  • VBUS voltage range
  • Processor logic levels VOH, VOL for EN and VIH, VIL for ACK pins
  • OTG power supply output voltage range

8.2.2.3 Application Curves

Refer to Application Curves in the previous section.