SLVSF72C
December 2019 – February 2021
TPD4S311
,
TPD4S311A
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Device Comparison Table
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings—JEDEC Specification
7.3
ESD Ratings—IEC Specification
7.4
Recommended Operating Conditions
7.5
Thermal Information
7.6
Electrical Characteristics
7.7
Timing Requirements
7.8
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
4-Channels of Short-to-VBUS Overvoltage Protection (CC1, CC2, SBU1, SBU2 Pins ): 24-VDC Tolerant
8.3.2
4-Channels of IEC 61000-4-2 ESD Protection (CC1, CC2, SBU1, SBU2 Pins)
8.3.3
CC1, CC2 Overvoltage Protection FETs 400-mA or 600-mA Capable for Passing VCONN Power
8.3.4
CC Dead Battery Resistors Integrated for Handling the Dead Battery Use Case in Mobile Devices
8.3.5
1.69-mm × 1.69-mm DSBGA Package
8.4
Device Functional Modes
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
VBIAS Capacitor Selection
9.2.2.2
Dead Battery Operation
9.2.2.3
CC Line Capacitance
9.2.2.4
Additional ESD Protection on CC and SBU Lines
9.2.2.5
FLT Pin Operation
9.2.2.6
How to Connect Unused Pins
9.2.3
Application Curves
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Documentation Support
12.1.1
Related Documentation
12.2
Receiving Notification of Documentation Updates
12.3
Support Resources
12.4
Trademarks
12.5
Electrostatic Discharge Caution
12.6
Glossary
13
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
YBF|16
MXBG442
Thermal pad, mechanical data (Package|Pins)
Orderable Information
slvsf72c_oa
slvsf72c_pm
8.2
Functional Block Diagram