SLVSF72C December   2019  – February 2021 TPD4S311 , TPD4S311A

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings—JEDEC Specification
    3. 7.3 ESD Ratings—IEC Specification
    4. 7.4 Recommended Operating Conditions
    5. 7.5 Thermal Information
    6. 7.6 Electrical Characteristics
    7. 7.7 Timing Requirements
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 4-Channels of Short-to-VBUS Overvoltage Protection (CC1, CC2, SBU1, SBU2 Pins ): 24-VDC Tolerant
      2. 8.3.2 4-Channels of IEC 61000-4-2 ESD Protection (CC1, CC2, SBU1, SBU2 Pins)
      3. 8.3.3 CC1, CC2 Overvoltage Protection FETs 400-mA or 600-mA Capable for Passing VCONN Power
      4. 8.3.4 CC Dead Battery Resistors Integrated for Handling the Dead Battery Use Case in Mobile Devices
      5. 8.3.5 1.69-mm × 1.69-mm DSBGA Package
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 VBIAS Capacitor Selection
        2. 9.2.2.2 Dead Battery Operation
        3. 9.2.2.3 CC Line Capacitance
        4. 9.2.2.4 Additional ESD Protection on CC and SBU Lines
        5. 9.2.2.5 FLT Pin Operation
        6. 9.2.2.6 How to Connect Unused Pins
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.7 Timing Requirements

MINNOMMAXUNIT
Power-On and Off Timings
tON_FETTime from Crossing Rising VPWR UVLO until CC and SBU OVP FETs are on. 1.33.5ms
tON_FET_DBTime from Crossing Rising VPWR UVLO until CC and SBU OVP FETs are on and the dead battery resistors are off. 5.79.5ms
dVPWR_OFF/dtMinimum slew rate allowed to guarantee CC and FETs turn off during a power off. -0.5V/µs
Over Voltage Protection
tOVP_RESPONSE_CCOVP response time on the CCx pins. Time from OVP asserted until OVP FETs turn off. 70ns
tOVP_RESPONSE_SBUOVP response time on the SBUx pins. Time from OVP asserted until OVP FETs turn off. 80ns
tOVP_RECOVERY_CCOVP recovery time on the CCx pins. Once an OVP has occurred, the minimum time duration until the CC FETs turn back on. OVP must be removed for CC FETs to turn back on. 0.93ms
tOVP_RECOVERY_CC_DBOVP recovery time on the CCx pins. Once an OVP has occurred, the minimum time duration until the CC FETs turn back on and the dead battery resistors turn off. OVP must be removed for CC FETs to turn back on. 5ms
tOVP_RECOVERY_SBUOVP recovery time on the SBUx pins. Once an OVP has occurred, the minimum time duration until the SBU FETs turn back on. OVP must be removed for SBU FETs to turn back on. 0.62ms
tOVP_FLT_ASSERTIONTime from OVP Asserted to /FLT assertion. FLT assertion is 10% of the maxmimum value. Set C_CCx or C_SBUx above the maxmimum OVP threshold. Start the time where it passes the typical OVP threshold value.20µs
tOVP_FLT_DEASSERTIONTime from CC FET turn on after an OVP to FLT deassertion. 5ms