SLVSH00 November   2024 TPD4S480

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings—IEC Specification
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 4-Channels of Short-to-VBUS Overvoltage Protection (CC1, CC2, SBU1, SBU2 Pins or CC1, CC2, DP, DM Pins): 63-VDC Tolerant
      2. 6.3.2 CC1, CC2 Overvoltage Protection FETs 600-mA Capable for Passing VCONN Power
      3. 6.3.3 CC Dead Battery Resistors Integrated for Handling the Dead Battery Use Case in Mobile Devices
      4. 6.3.4 EPR Adapter
        1. 6.3.4.1 VBUS Divider
        2. 6.3.4.2 EPR Blocking FET Gate Driver
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
        1. 7.2.1.1 EPR Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 VBIAS Capacitor Selection
        2. 7.2.2.2 Dead Battery Operation
        3. 7.2.2.3 CC Line Capacitance
        4. 7.2.2.4 Additional ESD Protection on CC and SBU Lines
        5. 7.2.2.5 FLT Pin Operation
        6. 7.2.2.6 How to Connect Unused Pins
      3. 7.2.3 EPR Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1.     52

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RUK|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.4.2 EPR Blocking FET Gate Driver

An NFET gate driver is integrated for controlling an external blocking FET. When in EPR mode the gate driver is disabled, isolating any non-EPR tolerant circuitry from VBUS. When in SPR mode the gate driver is enabled connecting low voltage components to VBUS.

Table 6-2 VBUS Divider States
EPR_EN VBUS Gate Driver State Description
0 < EPR_THRES_R Enabled SPR Operation
1 X Disabled EPR Operation
X > EPR_THRESH_R Disabled