SLLS685D July   2006  – September 2015 TPD6E001

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

RSE Package
10-Pin UQFN
Top View
TPD6E001 po_lls685.gif
N.C.- Not internally connected
RSF Package
12-Pin WQFN
Top View
TPD6E001 po_1_lls685.gif
N.C.- Not internally connected

Pin Functions

PIN TYPE DESCRIPTION
NAME RSE RSF
GND 5 5 GND Ground
IOx 1, 2, 3,
6, 7, 8		 1, 2, 3,
7, 8, 9		 I/O ESD-protected channel
N.C. 4, 9 4, 6, 10, 12 — Not internally connected
VCC 10 11 Power Power-supply input. Bypass VCC to GND with a 0.1-μF ceramic capacitor.
EP – EP GND Exposed pad. Connect to GND.